The physical limitations of complementary metal-oxide semiconductor (CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.
The complementary metal-oxide semiconductor (CMOS) technology has played a vital role in constructing integrated systems for the past four decades. This technology has provided the requirements of implementing high-density, high- speed and low-power very large scale integrated systems. However, the fundamental physical limits of this technology have been reached [
Traditional Boolean logic functions are simplified and expressed in two standard forms which are sum of products (SOP) and product of sums (POS) in terms of logic AND, OR and NOT gates. These standard forms are always produced using logic reduction methods that target CMOS technology. However, these methods are not efficient enough to produce simplified expressions in terms of logic majority or minority for post-CMOS nanotechnologies due to the complexity of multi-level majority and minority circuits. Since the function of minority gate is just the complement of majority gate, a minority logic network can be easily produced from its equivalent majority network. This process can be done by using De Morgan’s theorem which is based on the use of inverters. Thus, by having an efficient majority logic synthesis method, both majority and minority logic networks can be obtained.
The history of research in majority logic synthesis dates back to the 1960s. Karnaugh-map (K-map) [
Even though many majority/minority logic network synthesis methods have been proposed, none of these methods can synthesize optimal majority/minority logic networks for all cases. As the purpose of this paper is to provide a review of the best synthesis methods, we only concentrate on the multi-input multi-output majority/minority logic networks synthesis methods and do not discuss the limited methods.
The rest of the paper is organized as follows. In Section 2, we discuss some of majority/minority-based post-CMOS nanotechnologies and the implementation of their logic devices. Section 3 describes the best available comprehensive majority/minority logic synthesis methods. Section 4 compares the synthesis methods described in Section 3 and discusses experimental results using these methods. The paper is concluded in Section 5.
In this section, we review some post-CMOS nanotechnologies and the implementation of their majority and/or minority logic devices.
Quantum-dot cellular automata (QCA) technology is one of nanotechnologies that provide a new technique of computation information transformation. This technology uses a QCA majority gate as the basic device along with QCA wire and QCA inverter to implement logic circuits.
A QCA cell contains four quantum dots that are located at the corners of a square. By charging a cell with two free electrons, which tunnel between dots, there are only two states of electrons pairs that are energetically stable due to Coulombic interactions. The two configurations of electrical charges in a cell encode binary information. Each of these configurations has a different cell polarization. These polarizations are P = + 1 and P = − 1 which represent logic 1 and 0, respectively.
In QCA, a logic circuit is implemented using three primitive devices that are QCA wire, QCA inverter, and QCA majority logic gate. The construction of these devices is based on QCA cell which is the fundamental unit in QCA.
A QCA wire can be constructed by placing a group of cells next to each other as shown in
By placing cells in a diagonal position, the polarizations of these cells will be reversed. Based on this characteristic, the QCA inverter can be constructed as shown in
The function of a QCA majority gate is a three-input logic function given in (1). The majority function is to produce an output logic 1 if two or more of the three inputs ( x 1 , x 2 , x 3 ) are 1. Otherwise, it produces an output logic 0. The layout of QCA majority gate is shown in
M ( x 1 , x 2 , x 3 ) = x 1 x 2 + x 1 x 3 + x 2 x 3 (1)
By forcing one of the inputs ( x 1 , x 2 , x 3 ) in a three-input majority gate to logic 0 or 1, the gate will perform as a two-input logic AND or a two-input logic OR function as given in (2) and (3), respectively.
M ( x 1 , x 2 , 0 ) = x 1 x 2 (2)
M ( x 1 , x 2 , 1 ) = x 1 + x 2 (3)
In single electron tunneling (SET) technology, both majority and minority gates are used to implement logic circuits. A SET minority gate implements a three- input logic function given in (4). Since the minority function is just the complementary of majority function, it produces an output 0 if one or more of its inputs are 1. Otherwise, it produces an output 1.
m ( x 1 , x 2 , x 3 ) = x ′ 1 x ′ 2 + x ′ 1 x ′ 3 + x ′ 2 x ′ 3 (4)
By setting one of the three inputs of the minority gate as a logic 0 or 1, the gate implements a two-input logic NAND or two-input logic NOR gate, respectively [
m ( x 1 , x 2 , 0 ) = x ′ 1 + x ′ 2 = ( x 1 x 2 ) ′ (5)
m ( x 1 , x 2 , 1 ) = x ′ 1 x ′ 2 = ( x 1 + x 2 ) ′ (6)
A SET majority gate is constructed of three input capacitors, a balanced pair of SEBs, three output capacitors as shown in
A tunneling phase logic (TPL) minority gate is the basic unit used in TPL technology to implement logic circuits. As shown in
are different, they will neutralize each other and the reverse of the third waveform will be the output. However, if all input waveforms have the same phases, the output will be the reverse of these phases.
A spintronic majority gate (SMG) is a device that performs a three-input majority function. This device is implemented with a cross of ferromagnetic wires with a size of 140 × 140 nm [
An all spin logic (ASL) device is also spin based device [
A spin torque oscillator (STO) logic is a device that can perform a three-input majority function [
In spin wave device (SWD) technology, computation and information transformation occur via spin waves [
The process of computation and information transformation in nanomagnetic logic (NML) [
DNA technology is being considered as a possible alternative to silicon-based technologies especially for implantable medical devices. The small size, light weight, and compatibility with bio-signals of DNA technology show its ability of implementing logic circuits. Several researchers have introduced different designs of DNA majority gates [
In addition to the nanotechnologies discussed in this paper, other nanotechnologies such as graphene [
discussed earlier, the circuit has to be converted into its equivalent majority- or minority-based logic circuit.
As mentioned earlier, since minority logic is the complement of majority function, De Morgan’s theorem can be used to drive a minority logic network from its equivalent majority network. This process results in a minority network with the same number of majority gates and levels as in its equivalent majority network. This means that an efficient majority network synthesis method can be used to obtain both majority and minority networks. The simplified Boolean functions expressed in standard forms SOP and POS can be directly converted into majority or minority logic networks by implementing the majority AND/ OR mapping method. This method is to map each logic gate in the simplified Boolean functions to majority AND/OR gates. However, in most cases, this method does not results in optimal majority/minority expressions. In other words, the number of gates, levels, etc., used in majority/minority expressions obtained from the AND/OR mapping method are not the optimal results. For example, consider the majority function f = x 1 x 2 + x 1 x 3 + x 2 x 3 . By using the AND/OR mapping method, it requires five majority gates, three levels as n 1 = x 1 x 2 , n 2 = x 1 x 3 , n 3 = x 2 x 3 , n 4 = n 1 + n 2 , and f = n 3 + n 4 , whereas it can be realized with only one majority gate in one level, i.e., f = M ( x 1 , x 2 , x 3 ) . Therefore, an efficient majority/minority logic network synthesis is needed in order to generate optimal majority/minority logic networks. In the next section, we review the best existing comprehensive majority/minority logic synthesis methods in detail.
Several researchers have proposed different techniques for majority/minority logic synthesis. However, none of these techniques are capable of generating optimal majority or minority expressions in terms of gates, levels, inverters and gate inputs for all cases. In addition, only a few of these methods can be used for synthesizing multi-input multi-output majority/minority logic networks. These methods are discussed in detail as follows:
MALS is the first proposed comprehensive majority/minority logic network synthesis method that is capable of synthesizing multi-level multi-output majority/ minority logic networks. The input to MALS is a minimized algebraically factored multi-output combinational network, and the output is an equivalent majority logic network. The method starts by preprocessing and decomposing the input network such that each node in the decomposed network has at most three input variables. This process is done by using preprocessing and decomposition methods in SIS. The next step is to check each decomposed node to see whether it is a majority function. If so, the node will be converted and the process will move to check the next node. Otherwise, the node function will be checked if there is any common literal. If this is the case, the literal will be factored out and an AND/OR mapping is then performed on the factored function. If the node function has no common literal and it can be realized with less than four majority AND/OR gates, an AND/OR mapping will then be performed. Otherwise, the node will be converted into its equivalent majority expression with at most four majority gates in two levels using K-map. This procedure is accomplished by first getting the K-map of the logic function of the node. Next, the first majority function f1 is determined by finding the admissible pattern from the K-map of the node. Based on the K-map of the node and the first admissible pattern, the second admissible pattern is then found which gives the second majority function f2. Lastly, the third admissible pattern is found based on the K-map of the node and the first and the second admissible patterns. The third admissible pattern gives the third majority function f3. These three majority functions are determined such that the original node can be replaced with the majority function of these three functions as M ( f 1 , f 2 , f 3 ) .
Another comprehensive majority/minority logic network synthesis method was introduced by Kong et al. [
is to select the majority function with a minimum number of majority gates, gate inputs, and inverters from the selected majority functions that consist of expression groups and their complements. The last step is to check obtained majority expressions and see if there are repeated nodes. If so, these nodes will be removed and the majority network will be updated. This process keeps running until no repeated nodes exist.
One of the majority/minority logic network synthesis methods is MLUT-based method [
The three majority/minority synthesis methods discussed in this paper differ from each other in their preprocessing methods, decomposition methods, conversion techniques, and optimization targets: gates, levels, inverters, and gate inputs.
The first step in all three synthesis methods is preprocessing. This process is
Method | Preprocessing (r-feasible networks) | Decomposition | Conversion technique | Optimization targets | |||||
---|---|---|---|---|---|---|---|---|---|
Methods | r-feasible networks | Node reduction | Gates | Levels | Inverters | Gate inputs | |||
MALS [ |
r = 3 | 1 | r = 3 | No | K-map | Yes | No | No | No |
Kong’s [ |
r = 3 | 1, 2, 3, 4 | r = 3 | Yes | 40 Primitive functions | Yes | No | Yes | Yes |
MLUT [ |
r = 4 | 1, 2, 3, 4 | r = 2 , 3 , 4 | Yes | 90 Primitive functions | Yes | Yes | Yes | Yes |
used to simplify the input Boolean functions by removing the redundant terms and algebraically factoring the common terms out. For example, consider the Boolean function F = x 1 x ′ 2 + x 1 x 3 + x ′ 2 x 3 + x 1 x ′ 2 x 3 . This function is first simplified to F = x 1 x ′ 2 + x 1 x 3 + x ′ 2 x 3 . Then, the common terms are factored out and the function is simplified to F = ( x ′ 2 + x 3 ) x 1 + x ′ 2 x 3 . In all algorithms, this process is done by using the simplification and factorization methods in SIS. However, the preprocessing method used in MLUT is improved by performing the operations of kernel and cube extraction for four-feasible networks instead of three-feasible networks as used in MALS and Kong’s method.
Although, the preprocessing method provides simplified Boolean functions in terms of logic AND, OR and NOT, these functions are not expressed properly to be converted into their equivalent majority expressions for some cases. To demonstrate this point, consider the same function that we used for simplification. After removing the redundant term, the function is expressed by F = x 1 x ′ 2 + x 1 x 3 + x ′ 2 x 3 . It can be seen that this function is expressed as a majority function which can be realized with only one majority gate in one level, i.e., F = M ( x 1 , x ′ 2 , x 3 ) . However, if the common terms are algebraically factored out, i.e., F = ( x ′ 2 + x 3 ) x 1 + x ′ 2 x 3 , the function will have a different expression which can result in an equivalent majority expression with more than one majority gate and one level. This specific example may not fall in this category due to its simplicity. However, this case can occur especially while processing large circuits which can cause a large change in the final result.
For decomposition, MALS uses method 1 in
For converting the decomposed networks into their equivalent majority expressions, each method uses a different technique. The MALS method uses K-map to obtain one-level majority functions f 1 , f 2 and f 3 for each node, such that the function can be represented as M ( f 1 , f 2 , f 3 ) . This method can generate only one admissible majority expression for a given Boolean function. This is considered as a drawback for this method. Therefore, this technique does not guarantee that it results in optimal majority expressions. In Kong’s method, the process of converting the function of a node is based on forty optimal majority expressions. If the Boolean function belongs to these forty expressions, it is converted into its corresponding majority expression. Otherwise, all admissible three-expression groups from the forty expressions are found such that the function of the node can be represented as a majority function of the three expressions. This conversion technique is also used in MLUT. However, this method is based on ninety primitive functions instead of forty as used in Kong’s method. These primitives are the equivalent majority expressions for all possible four-variable Boolean functions. Each node in the decomposed network is replaced with its equivalent majority expressions if it has a corresponding expression. Otherwise, a combination of three majority expressions is chosen from the ninety expressions such that the function of the node can be represented as the majority function of the chosen three expressions.
Since the gate count and level count determine the latency and the size of a majority/minority circuit, they are the most important factors that play an essential role in enhancing performance. Therefore, by reducing the number of gates and the number of levels, the performance can be improved. In the three comprehensive synthesis methods (MALS, Kong’s, and MLUT), the optimization is targeted to reduce either the number of gates or levels. In MALS and Kong’s method, the gate count reduction is taken as the first priority for optimization. However, in MLUT, either the number of gates or levels can be taken as the first priority. In addition to the number of gates and level count, there are other factors that can play an essential role in providing further scaling down of feature sizes of a generated majority circuit. One of these factors is inverter count. In some nanotechnologies, the implementation of an inverter requires a larger area than a majority gate. For example, in QCA technology, the implementation of an inverter requires seven QCA cells as shown in
In this section, we demonstrate an overall comparison between the results obtained from the existing synthesis methods. In
For Boolean functions with more than three variables, we compare the results of 40 Microelectronics Center North Carolina benchmark circuits [
Standard function | Method | Majority expression | Gates | Levels | Inverters | Gate inputs |
---|---|---|---|---|---|---|
F = x 1 x 2 + x ′ 1 x ′ 2 x 3 | AND/OR mapping | M ( M ( M ( x ′ 1 , 0 , x ′ 2 ) , 0 , x 3 ) , 1 , M ( x 1 , 0 , x 2 ) ) | 4 | 3 | 2 | 8 |
[ |
M ( M ( M ( x ′ 1 , 0 , x ′ 2 ) , 0 , x 3 ) , 1 , M ( x 1 , 0 , x 2 ) ) | 4 | 3 | 2 | 8 | |
[ |
M ( M ( x ′ 1 , 1 , x 2 ) , M ( x 1 , 0 , x 2 ) , M ( x ′ 2 , 0 , x 3 ) ) | 4 | 2 | 2 | 9 | |
[ |
M ( M ( x 1 , 0 , x 2 ) , M ( x 1 , 1 , x 2 ) ′ , M ( x 1 , 1 , x 3 ) ) | 4 | 2 | 1 | 9 | |
[ |
M ( M ( x ′ 1 , 1 , x 2 ) , M ( x 1 , x ′ 2 , x 3 ) , M ( x 1 , 0 , x 2 ) ) | 4 | 2 | 2 | 10 | |
[ |
M ( M ( x 1 , 0 , x 2 ) , M ( x 1 , 1 , x 2 ) ′ , M ( x 1 , 1 , x 3 ) ) | 4 | 2 | 1 | 9 | |
F = x 1 x 2 x 3 + x 2 x ′ 3 + x 1 x ′ 2 x ′ 3 | AND/OR mapping | M ( M ( M ( M ( x 1 , 0 , x 2 ) , 0 , x 3 ) , 0 , M ( M ( x ′ 1 , 0 , x 2 ) , 0 , x ′ 3 ) ) , 0 , M ( M ( x 1 , 0 , x ′ 2 ) , 0 , x ′ 3 ) ) | 8 | 4 | 4 | 16 |
[ |
M ( M ( x 1 , 0 , x 3 ) , M ( x 1 , x 2 , x ′ 3 ) , M ( x ′ 1 , x ′ 2 , x ′ 3 ) ) | 4 | 2 | 4 | 11 | |
[ |
M ( M ( M ( x 1 , x 2 , x 3 ) , 1 , x 1 ) ′ , x 3 , M ( x 1 , x 2 , x ′ 3 ) ) | 4 | 3 | 2 | 11 | |
[ |
M ( M ( x 1 , x 2 , x ′ 3 ) , M ( x ′ 1 , 0 , x ′ 3 ) , M ( x 1 , x ′ 2 , x 3 ) ) | 4 | 2 | 4 | 11 | |
[ |
M ( M ( x 1 , x 2 , x ′ 3 ) , M ( x 1 , x ′ 2 , x 3 ) , M ( x ′ 1 , 0 , x 2 ) ) | 4 | 2 | 3 | 11 | |
[ |
M ( M ( x 1 , 0 , x 3 ) , M ( x 1 , x 2 , x 3 ) ′ , M ( x 1 , x 2 , x ′ 3 ) ) | 4 | 2 | 2 | 11 | |
F = x 1 + x 2 x 3 | AND/OR mapping | M ( M ( x 2 , 0 , x 3 ) , 1 , x 1 ) | 2 | 2 | 0 | 4 |
[ |
M ( M ( x 2 , 0 , x 3 ) , 1 , x 1 ) | 2 | 2 | 0 | 4 | |
[ |
M ( M ( x 1 , 1 , x 3 ) , x 1 , x 2 ) | 2 | 2 | 0 | 5 | |
[ |
M ( M ( x 2 , 0 , x 3 ) , 1 , x 1 ) | 2 | 2 | 0 | 4 | |
F = x 1 x 2 + x ′ 2 x 3 | AND/OR mapping | M ( M ( x 1 , 0 , x 2 ) , 1 , M ( x ′ 2 , 0 , x 3 ) ) | 3 | 2 | 1 | 6 |
[ |
M ( M ( x 1 , 0 , x 2 ) , 1 , M ( x ′ 2 , 0 , x 3 ) ) | 3 | 2 | 1 | 6 | |
[ |
M ( M ( x 1 , 1 , x 2 ) ′ , x 1 , M ( x 2 , 1 , x 3 ) ) | 3 | 2 | 1 | 7 | |
[ |
M ( M ( x 1 , 0 , x 2 ) , 1 , M ( x ′ 2 , 0 , x 3 ) ) | 3 | 2 | 1 | 6 | |
F = x 1 x 2 x 3 + x ′ 1 x ′ 2 x ′ 3 | AND/OR mapping | M ( M ( M ( x 1 , 0 , x 2 ) , 0 , x 3 ) , 1 , M ( M ( x ′ 1 , 0 , x ′ 2 ) , 0 , x ′ ) ) | 5 | 3 | 3 | 10 |
[ |
M ( M ( M ( x 1 , 0 , x 2 ) , 0 , x 3 ) , 1 , M ( M ( x ′ 1 , 0 , x ′ 2 ) , 0 , x ′ ) ) | 5 | 3 | 3 | 10 | |
[ |
M ( M ( x ′ 1 , 1 , x 2 ) , M ( x ′ 2 , 0 , x ′ 3 ) , M ( x 1 , 0 , x 3 ) ) | 4 | 2 | 3 | 9 | |
[ |
M ( M ( x 1 , 1 , x 2 ) ′ , M ( x 2 , 0 , x 3 ) , M ( x ′ 1 , 0 , x ′ 3 ) ) | 4 | 2 | 2 | 9 | |
[ |
M ( M ( x 1 , 1 , x 2 ) , M ( x 2 , 1 , x 3 ) ′ , M ( x ′ 1 , 1 , x 3 ) ) | 4 | 2 | 2 | 9 |
F = x 1 x 2 + x 2 x 3 + x ′ 1 x ′ 2 x ′ 3 | AND/OR mapping | M ( M ( M ( x 1 , 0 , x 2 ) , 1 , M ( x 2 , 0 , x 3 ) ) , 1 , M ( M ( x ′ 1 , 0 , x ′ 2 ) , 0 , x ′ 3 ) ) | 6 | 3 | 3 | 12 |
---|---|---|---|---|---|---|
[ |
M ( M ( M ( x 1 , 1 , x 3 ) , 0 , x 2 ) , 1 , M ( M ( x ′ 2 , 0 , x ′ 3 ) , 0 , x ′ 1 ) ) | 5 | 3 | 3 | 10 | |
[ |
M ( M ( x 1 , x 2 , x 3 ) , M ( x ′ 1 , 1 , x ′ 2 ) , M ( x ′ 2 , 0 , x ′ 3 ) ) | 4 | 2 | 3 | 10 | |
[ |
M ( M ( x 1 , x 2 , x 3 ) , M ( x ′ 1 , 0 , x ′ 2 ) , M ( x ′ 2 , 1 , x ′ 3 ) ) | 4 | 2 | 3 | 10 | |
[ |
M ( M ( x ′ 1 , 1 , x 2 ) , M ( x 2 , 1 , x 3 ) ′ , M ( x 1 , x 2 , x 3 ) ) | 4 | 2 | 2 | 10 | |
F = x 1 x 2 x 3 + x ′ 1 x ′ 2 x 3 + x 1 x ′ 2 x ′ 3 + x ′ 1 x 2 x ′ 3 | AND/OR mapping | M ( M ( M ( M ( x 1 , 0 , x 2 ) , 0 , x 3 ) , 1 , M ( M ( x ′ 1 , 0 , x ′ 2 ) , 0 , x 3 ) ) , 1 , M ( M ( M ( x 1 , 0 , x ′ 2 ) , 0 , x ′ 3 ) , 1 , M ( M ( x ′ 1 , 0 , x 2 ) , 0 , x ′ 3 ) ) ) | 11 | 5 | 6 | 22 |
[ |
M ( M ( x ′ 1 , x 2 , x 3 ) , x ′ 3 , M ( x 1 , x ′ 2 , x 3 ) ) | 3 | 2 | 3 | 9 | |
[ |
M ( M ( x 1 , x 2 , x 3 ) ′ , x 3 , M ( x 1 , x 2 , x ′ 3 ) ) | 3 | 2 | 2 | 9 | |
[ |
M ( M ( x ′ 1 , x 2 , x 3 ) , M ( x 1 , x 2 , x ′ 3 ) , M ( x 1 , x ′ 2 , x 3 ) ) | 4 | 2 | 3 | 12 | |
[ |
M ( M ( x 1 , x 2 , x 3 ) ′ , x 1 , M ( x ′ 1 , x 2 , x 3 ) ) | 3 | 2 | 2 | 9 | |
F = x 1 x 2 x 3 + x 1 x ′ 2 x ′ 3 | AND/OR mapping | M ( M ( M ( x 1 , 0 , x 2 ) , 0 , x 3 ) , 1 , M ( M ( x 1 , 0 , x ′ 2 ) , 0 , x ′ 3 ) ) | 5 | 3 | 2 | 10 |
[ |
M ( M ( x 1 , x 2 , x ′ 3 ) , 0 , M ( x 1 , x ′ 2 , x 3 ) ) | 3 | 2 | 2 | 8 | |
[ |
M ( M ( x 2 , 0 , x 3 ) , x 1 , M ( x 2 , 1 , x 3 ) ′ ) | 3 | 2 | 1 | 7 | |
[ |
M ( M ( M ( x ′ 2 , 0 , x ′ 3 ) , 1 , M ( x 2 , 0 , x 3 ) ) , 0 , x 1 ) | 4 | 3 | 2 | 8 | |
[ |
M ( M ( x 2 , 0 , x 3 ) , x 1 , M ( x 2 , 1 , x 3 ) ′ ) | 3 | 2 | 1 | 7 |
Benchmark | AND/OR mapping |
MALS [ |
Kong’s [ |
MLUT [ |
Reduction% | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Gate priority | Level priority |
MALS [ |
Kong’s [ |
MLUT [ |
MLUT [ |
|||||||||||||
Gates | Levels | Gates | Levels | Gates | Levels | Gates | Levels | Levels | Gates | Gates | Levels | Gates | Levels | Gates | Levels | Levels | Gates | |
b1 | 9 | 3 | 9 | 3 | 7 | 2 | 6 | 2 | 2 | 6 | 0.0 | 0.0 | 22.2 | 33.3 | 33.3 | 33.3 | 33.3 | 33.3 |
cm42a | 21 | 2 | 21 | 2 | 18 | 2 | 18 | 2 | 2 | 18 | 0.0 | 0.0 | 14.3 | 0.0 | 14.3 | 0.0 | 0.0 | 14.3 |
decod | 28 | 3 | 28 | 3 | 28 | 3 | 28 | 3 | 3 | 28 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
cm82a | 50 | 7 | 16 | 8 | 7 | 3 | 6 | 3 | 3 | 6 | 68.0 | −14.3 | 86.0 | 57.1 | 88.0 | 57.1 | 57.1 | 88.0 |
majority | 12 | 5 | 6 | 5 | 6 | 4 | 5 | 4 | 3 | 6 | 50.0 | 0.0 | 50.0 | 20.0 | 58.3 | 20.0 | 40.0 | 50.0 |
z4ml | 71 | 10 | 27 | 8 | 9 | 4 | 9 | 4 | 4 | 9 | 62.0 | 20.0 | 87.3 | 60.0 | 87.3 | 60.0 | 60.0 | 87.3 |
9symml | 276 | 15 | 216 | 12 | 47 | 10 | 45 | 12 | 10 | 47 | 21.7 | 20.0 | 83.0 | 33.3 | 84.0 | 20.0 | 33.3 | 73.2 |
ldd | 91 | 9 | 73 | 13 | 67 | 7 | 67 | 7 | 7 | 67 | 19.8 | −44.4 | 26.4 | 22.2 | 26.4 | 22.2 | 22.2 | 26.4 |
alu2 | 495 | 15 | 354 | 18 | 340 | 18 | 329 | 18 | 16 | 347 | 28.5 | −20.0 | 31.3 | −20.0 | 33.5 | −20.0 | −6.7 | 29.9 |
x2 | 49 | 6 | 42 | 8 | 37 | 7 | 34 | 7 | 6 | 36 | 14.3 | −33.3 | 24.5 | −16.7 | 30.6 | −16.6 | 0.0 | 26.5 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
cm152a | 31 | 5 | 21 | 5 | 21 | 6 | 17 | 6 | 6 | 17 | 32.3 | 0.0 | 32.3 | −20.0 | 45.2 | −20.0 | −20.0 | 45.2 |
cm85a | 80 | 10 | 34 | 10 | 26 | 6 | 19 | 6 | 6 | 19 | 57.5 | 0.0 | 67.5 | 40.0 | 76.3 | 40.0 | 40.0 | 76.3 |
cm151a | 56 | 8 | 42 | 8 | 23 | 7 | 20 | 7 | 7 | 20 | 25.0 | 0.0 | 58.9 | 12.5 | 64.3 | 12.5 | 12.5 | 64.3 |
cm162a | 57 | 7 | 46 | 9 | 41 | 7 | 36 | 9 | 7 | 41 | 19.3 | −28.6 | 28.1 | 0.0 | 36.8 | -28.6 | 0.0 | 28.1 |
cu | 61 | 8 | 46 | 7 | 40 | 7 | 39 | 7 | 6 | 40 | 24.6 | 12.5 | 34.4 | 12.5 | 36.1 | 12.5 | 25.0 | 34.4 |
cm163a | 52 | 7 | 42 | 9 | 38 | 7 | 32 | 7 | 7 | 32 | 19.2 | −28.6 | 26.9 | 0.0 | 38.5 | 0.0 | 0.0 | 38.5 |
cmb | 44 | 4 | 44 | 5 | 28 | 4 | 26 | 4 | 4 | 26 | 0.0 | −25.0 | 36.4 | 0.0 | 40.1 | 0.0 | 0.0 | 40.1 |
pm1 | 49 | 6 | 45 | 7 | 35 | 6 | 32 | 6 | 6 | 32 | 8.2 | −16.7 | 28.6 | 0.0 | 34.7 | 0.0 | 0.0 | 34.7 |
tcon | 24 | 2 | 24 | 2 | 24 | 2 | 24 | 2 | 2 | 24 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
vda | 856 | 13 | 738 | 14 | 700 | 15 | 670 | 14 | 14 | 670 | 13.8 | −7.7 | 18.2 | −15.4 | 21.7 | −7.7 | −7.7 | 21.7 |
pcle | 78 | 9 | 67 | 8 | 62 | 8 | 62 | 8 | 8 | 62 | 14.1 | 11.1 | 20.5 | 11.1 | 20.5 | 11.1 | 11.1 | 20.5 |
sct | 86 | 7 | 72 | 10 | 65 | 6 | 65 | 6 | 6 | 65 | 16.3 | −42.9 | 24.4 | 14.3 | 24.4 | 14.3 | 14.3 | 24.4 |
cc | 49 | 5 | 44 | 5 | 43 | 5 | 43 | 5 | 5 | 43 | 10.2 | 0.0 | 12.2 | 0.0 | 12.2 | 0.0 | 0.0 | 12.2 |
cm150a | 54 | 8 | 46 | 8 | 46 | 9 | 37 | 6 | 6 | 37 | 14.8 | 0.0 | 14.8 | −12.5 | 31.5 | 25.0 | 25.0 | 31.5 |
mux | 55 | 7 | 46 | 7 | 46 | 9 | 37 | 6 | 6 | 37 | 16.4 | 0.0 | 16.6 | −28.6 | 32.7 | 14.3 | 14.3 | 32.7 |
ttt2 | 187 | 11 | 154 | 11 | 145 | 11 | 144 | 10 | 10 | 144 | 17.6 | 0.0 | 17.6 | 0.0 | 22.5 | 9.0 | 9.0 | 23.0 |
i1 | 54 | 7 | 41 | 8 | 36 | 6 | 35 | 6 | 6 | 35 | 24.0 | −14.3 | 33.3 | 14.3 | 35.2 | 14.3 | 14.3 | 35.2 |
lal | 123 | 7 | 95 | 9 | 82 | 8 | 64 | 9 | 8 | 82 | 22.8 | −28.6 | 33.3 | −14.3 | 48.0 | −28.6 | −14.3 | 33.3 |
pcler8 | 107 | 11 | 90 | 8 | 80 | 9 | 80 | 9 | 8 | 90 | 15.9 | 27.3 | 25.2 | 18.2 | 25.2 | 18.2 | 27.3 | 15.9 |
frg1 | 196 | 17 | 111 | 23 | 105 | 18 | 102 | 17 | 17 | 102 | 43.4 | −35.3 | 46.4 | −5.9 | 48.0 | 0.0 | 0.0 | 48.0 |
c8 | 124 | 8 | 115 | 8 | 112 | 7 | 108 | 8 | 7 | 112 | 10.2 | 0.0 | 12.5 | 12.5 | 15.6 | 0.0 | 12.5 | 12.5 |
term1 | 352 | 12 | 174 | 16 | 106 | 11 | 89 | 10 | 10 | 89 | 50.1 | −33.3 | 69.9 | 8.3 | 74.7 | 16.7 | 16.7 | 74.7 |
unreg | 84 | 5 | 84 | 4 | 84 | 5 | 84 | 5 | 5 | 84 | 0.0 | 20.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
k2 | 1602 | 18 | 1313 | 19 | 1301 | 19 | 1193 | 19 | 19 | 1193 | 18.0 | −5.6 | 18.8 | −5.6 | 25.5 | −5.6 | −5.6 | 25.5 |
cht | 121 | 4 | 120 | 4 | 120 | 4 | 120 | 4 | 4 | 120 | 0.8 | 0.0 | 0.8 | 0.0 | 0.8 | 0.0 | 0.0 | 0.8 |
x1 | 573 | 12 | 320 | 13 | 264 | 11 | 253 | 11 | 11 | 253 | 44.2 | −8.3 | 53.9 | 8.3 | 55.8 | 8.3 | 8.3 | 55.8 |
example2 | 285 | 9 | 259 | 9 | 247 | 10 | 241 | 9 | 9 | 241 | 9.1 | 0.0 | 13.3 | −11.1 | 15.4 | 0.0 | 0.0 | 15.4 |
apex6 | 984 | 16 | 701 | 14 | 662 | 17 | 662 | 17 | 15 | 677 | 28.8 | 12.5 | 32.7 | −6.3 | 32.7 | −6.3 | 6.3 | 31.2 |
frg2 | 759 | 14 | 672 | 15 | 582 | 14 | 568 | 15 | 13 | 600 | 11.5 | −7.1 | 23.3 | 0.0 | 25.2 | −7.1 | 7.1 | 20.9 |
i2 | 395 | 14 | 209 | 18 | 209 | 13 | 209 | 13 | 13 | 209 | 47.0 | −28.6 | 47.0 | 7.1 | 47.0 | 7.1 | 7.1 | 47.0 |
Average reduction% | 22.0% | −7.5% | 31.8% | 5.7% | 36.1% | 6.9% | 11.1% | 34.3% |
as well as 6.9% in level counts, whereas Kong’s method and MALS have an average reduction of 31.8% and 22.0% in the number of gates, respectively. When the MLUT method is targeted to optimize the level counts, there is an average reduction of 11.1% in the number of levels as well as 34.3% in the number of gates, whereas Kong’s method and MALS have an average reduction of 5.7% and −7.5% in level counts, respectively. It can be noticed that all methods give better average reduction results for gates and levels except the MALS method which results in a worse average reduction for level counts as compared to the AND/OR mapping method. Even though the MLUT method results in the highest average reduction for gate and level counts compared to other methods, it does not result in the optimal majority networks for some circuits. For example, the obtained majority network for the benchmark circuit cm152a using MLUT when targeted to optimize either majority gates or levels, requires six levels, whereas it can be realized with five levels as obtained from Kong’s method.
As a result, it can be observed from
Even though these methods result in the best majority networks in terms of some or all optimization factors for all cases, these networks are not guaranteed to be optimal especially while synthesizing multi-output Boolean functions. The process of selecting the optimal majority network for multi-output Boolean functions is not considered in any of the three synthesis methods, which is a very
Method | Decomposition | Optimization targets | ||||||
---|---|---|---|---|---|---|---|---|
Gates | Levels | Inverters | Gate inputs | Gates | Levels | Inverters | Gate inputs | |
MALS [ |
No | No | No | No | No | No | No | No |
Kong’s [ |
Yes | Yes | Yes | No | No | No | No | No |
MLUT [ |
Yes | Yes | Yes | No | Yes | No | Yes | No |
serious drawback. For a multi-output Boolean function, by synthesizing the equivalent majority expression for each output separately, which is performed in the three methods, the obtained majority expression can be the optimal in terms of all optimization factors for this output. However, the final majority network realized from these expressions is only optimal in terms of levels, which is the maximum number of levels used in these expressions. For the number of majority gates, inverters, and gate inputs, the final network is not always the optimal solution in terms of these factors. In other words, the number of gates, inverters, and gate inputs used in a majority network obtained from one of these methods for a multi-output Boolean network can be further reduced. To clarify this point, consider a Boolean network N with two outputs, i.e., F = x 1 x 2 x 3 + x ′ 1 x ′ 3 + x 1 x ′ 2 x ′ 3 and G = x 1 x 2 x 3 + x ′ 1 x ′ 2 x 3 . For the output F, one of its equivalent optimal majority expressions is F = M ( M ( x 1 , 0 , x 3 ) , M ( x 1 , x 2 , x 3 ) ′ , M ( x 1 , x 2 , x ′ 3 ) ) . For the output G, two of its equivalent majority expressions are
G 1 = M ( M ( x 1 , x 2 , x 3 ) ′ , x 3 , M ( x 1 , x 2 , x ′ 3 ) ) and
G 2 = M ( M ( x 1 , x 2 , x 3 ) ′ , x 1 , M ( x ′ 1 , x 2 , x 3 ) ) . It can be noticed that both majority
expressions for the output G have the same number of gates, levels, inverters, and gate inputs as 3, 2, 2, and 9, respectively. Now, the final majority network for N can be realized by selecting either majority expressions ( F , G 1 ) or ( F , G 2 ) . However, these networks are different in terms of some optimization factors. For the network ( F , G 1 ) , it has 5 gates, 2 levels, 2 inverters, and 14 gate inputs, whereas the second network ( F , G 2 ) has 6 gates, 2 levels, 3 inverters, and 16 gate inputs. From the two solutions, it can be seen that the number of levels is the only factor that does not change. However, the second network ( F , G 1 ) has the minimum number of gates, inverters, and gate inputs. Therefore, the best solution for network N is ( F , G 1 ) . Consequently, it can be seen that this is an important process that can provide further reduction and give better results in terms of different optimization factors.
As discussed earlier, since the different characteristics of nanotechnologies and their logic devices implementations can affect the optimization priorities given to different factors such as gates, levels, inverters, etc., a majority/minority logic network generated from the existing synthesis methods is not guaranteed to be the best solution for all nanotechnologies. Therefore, there is a strong need for developing an efficient majority/minority logic synthesis method that can synthesize the optimal majority/minority networks in terms of all optimization factors for any majority/minority-based nanotechnology.
Due to the physical limitations of CMOS technology, many emerging nanoscale technologies such as quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., have been proposed and considered as possible replacements for CMOS. As known, CMOS technology uses logic NAND, NOR and NOT gates to implement circuits. However, in post-CMOS nanotechnologies, majority and/or minority gates are the fundamental logic units used to implement Boolean functions. Since traditional reduction methods cannot result in optimal majority or minority logic networks, several papers have introduced different synthesis methods based on different principles. In this paper, we give a comprehensive review of majority/minority logic network synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. We also compare and discuss the obtained results from these methods based on different optimization factors such as the number of gates, the number of levels, etc. From this comparison, we observe that the existing techniques can give sub- optimal solutions. However, none of these methods results in the optimal majority/minority logic networks in terms of all optimization factors for all cases.
For future work in the majority/minority logic synthesis methods, it is suggested that the synthesis method should be developed to synthesis the equivalent majority and minority logic circuits for multi-input multi-output Boolean functions based on optimization techniques that can lead to optimal majority/minority circuits for more than four-feasible networks. In addition, as discussed previously, for a multi-output Boolean function, by generating the optimal majority circuit for each output Boolean function separately, the final majority circuit may not always be optimal. Therefore, it is better to synthesize the majority or minority circuit for any output function with consideration of the other output Boolean functions. Moreover, it suggested that the synthesis method should be developed to generate the optimal majority circuit in terms of all optimization factors based on the given priorities. By developing a method that can synthesize the majority circuits based on different priorities such as gates, levels, inverters, and gate inputs, the method can be used to generate the equivalent circuits for any majority and/or minority-based nanotechnologies.
The authors are thankful to the anonymous reviewers for their comments and suggestions to improve the paper.
Almatrood, A. and Singh, H. (2017) A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies. Engineering, 9, 890-915. https://doi.org/10.4236/eng.2017.910054