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Multilevel inverters are gaining popularity in high power applications. This paper proposes a new ladder type structure of cascaded three - phase multilevel inverter with reduced number of power semiconductor devices which is used to drive the induction motor. The ultimate aim of the paper is to produce multiple output levels with minimum n umber of semiconductor devices. This paper uses only 11 switches along with 3 diodes and 4 asymmetrical sources to produce an output voltage of 21 levels. The modulation technique plays a major role in commutation of the switches. Here we implement the multicarrier level shifting pulse width modulation technique to produce the commutation signals for the inverter. The proposed multilevel inverter is used to drive the three - phase induction motor. The mathematical modeling of three - phase induction motor is done using Simulink. Furthermore the PI and fuzzy logic controllers are also used to produce the reference waveform of the level shifting technique which in turn produces the commutation signals of the proposed multilevel converter. The controllers are used to control the speed of the induction motor. The effectiveness of the proposed system is proved with the help of simulation. The simulation is performed in MATLAB/Simulink. From the simulation results, it shows that the proposed multilevel inverter works properly to generate the multilevel output waveform with minimum n umber of semiconductor devices. The PI and fuzzy logic controller performance s are evaluated using the results which indicate that with the help of controllers the harmonics has been reduced and the speed control of induction motor is achieved under different loading conditions.

In recent years the energy demand is moving on increasing toward generating power with renewable energy source that may be dispersed in a wide area, and most of them are renewable, as they have greater advantages due to their environmentally friendly nature. The solar can be used by all in universe which doesn’t need more investigations of producing electricity. This leads to research in multilevel inverters. The multilevel inverters are classified into three types namely:

・ Diode clamped multilevel inverters;

・ Flying capacitor multilevel inverter;

・ Cascaded H bridge multilevel inverter.

Of these the cascaded H bridge multilevel inverter topologies give better results. The research goes on increasing to propose a new structure of inverter with reduced semiconductor devices with increased multilevel at the output waveform. In [

In [

From all the above analysis we conclude that the researches have been done on the control circuitry of the multilevel inverter. But the structure of inverter remains same. On increasing the levels the structure becomes more complex and bigger in size reducing the efficiency of the system.

Here we propose a new structural multilevel inverter to produce multiple levels at the output voltage with minimum number of power semiconductor devices. The proposed system is used to drive the induction motor and the performance of induction motor is analyzed. The PI and fuzzy controllers are also used to produce the modulation signals; also the controllers have been implemented for speed control of induction motor. The multi carrier level shifting PWM has also been implemented. Hence the THD is reduced lot with minimum number of devices with low switching noise.

The proposed multilevel inverter uses the ladder type connection of switches and diodes along with the voltage sources. In this topology we use asymmetrical voltage sources which may obtained from battery or from renewable energy sources like biomass, solar etc. the asymmetric dc voltage sources are incrementing in nature in the order of n, 2n, 3n, 4n, ∙∙∙ Where n = lowest DC voltage source magnitude.

The structure of proposed multilevel inverter is shown in

topology to generate 21 level voltage output. The operation of the proposed asymmetric multilevel inverter is explained with the help of _{DC}” be the number of DC sources or stages and the associated number of output voltage level can be calculated by using the equation,

The number of switches used in this topology is given by the equation,

The number of bypassed diodes used in this topology is given by the equation,

Therefore if we use 4 dc sources along with 3 diodes and seven semiconductor power switches we can capable of producing 21 voltage levels at the output. The proposed system consist of two parts namely main inverter and auxiliary inverter.

From

Cascade H-Bridge for 21 output levels | Proposed inverter for 21 output levels | |||
---|---|---|---|---|

Single phase | Three-phase | Single phase | Three-phase | |

Switches | 40 | 120 | 11 | 33 |

Diodes | - | - | 3 | 9 |

DC sources | 10 | 40 | 4 | 12 |

number of semiconductor devices when compared to the conventional one. Since the switching devices are reduced to a great extent the switching losses is also reduced which increases the effectiveness of the system.

Modes of OperationMODE-1:

In mode the switch s1 alone conducts. The current flows through s1, the source V1, the diode d1, d2 and d3 to produce the voltage of 1Vdc. The circuit is shown in

MODE-2:

In mode the switch s3 alone conducts. The current flows through s3, the source V2, the diode d2 and d3 to produce the voltage of 2Vdc. The circuit is shown in

MODE-3:

In mode the switch s5 alone conducts. The current flows through s5, the source V3, the diode d3 to produce the voltage of 3Vdc. The circuit is shown in

MODE-4:

In mode the switch s7 alone conducts. The current flows through s7 and the source V4 to produce the voltage of 4Vdc. The circuit is shown in

MODE-5:

In mode the switch s1 and s6 conducts. The current flows through s1, the source Vdc, the diode d1 and d2, the switch S6 and the voltage source 4Vdc. Hence it produce the voltage level of 5Vdc (Vdc + 4Vdc = 5Vdc) at the output. The circuit is shown in

MODE-6:

In mode the switch s3 and s6 conducts. The current flows through s3, the source 2Vdc, the diode d2, the switch S6 and the voltage source 4Vdc. Hence it produce the

voltage level of 6Vdc (2Vdc + 4Vdc = 6Vdc) at the output. The circuit is shown in

MODE-7:

In mode the switch s5 and s6 conducts. The current flows through s5, the source 3Vdc, the switch S6 and the voltage source 4Vdc. Hence it produce the voltage level of 7Vdc (3Vdc + 4Vdc = 7Vdc) at the output. The circuit is shown in

MODE-8:

In mode the switch s1, s4 and s6 conducts. The current flows through s1, the source 1Vdc, the diode D1, the switch S4, the voltage source 3Vdc, the switch s6 and the voltage source 4Vdc. Hence it produce the voltage level of 8Vdc (1Vdc + 3Vdc + 4Vdc = 8Vdc) at the output. The circuit is shown in

MODE-9:

In mode the switch s3, s4 and s6 conducts. The current flows through s3, the source 2Vdc, the switch S4, the voltage source 3Vdc, the switch s6 and the voltage source 4Vdc. Hence it produce the voltage level of 9Vdc (2Vdc + 3Vdc + 4Vdc = 9Vdc) at the output. The circuit is shown in

MODE-10:

In mode the switch s1, s2, s4 and s6 conducts. The current flows through s1, the source 1Vdc, the switch S2, the voltage source 2Vdc, the switch S4, the voltage source 3Vdc, the switch s6 and the voltage source 4Vdc. Hence it produce the voltage level of 10Vdc (1Vdc + 2Vdc + 3Vdc + 4Vdc = 10Vdc) at the output. The circuit is shown in

MODE-11:

In this mode all the switches are in off state. Therefore the output voltage is zero.

The Main inverter can generate only zero and positive voltage levels as shown in

The output voltage of Main inverter is always zero and positive only. To operate as an inverter, it is necessary to change the voltage polarity in every half cycle. For this purpose, the output of the Main inverter is fed to the H-Bridge inverter circuit which is called as the auxiliary inverter. The auxiliary inverter converters the main inverter positive voltages into positive and negative outputs. The block diagram of the proposed inverter is shown in

S. No. | Modes | Switching states | Output voltage level | ||||||
---|---|---|---|---|---|---|---|---|---|

S1 | S2 | S3 | S4 | S5 | S6 | S7 | |||

1 | MODE-1 | ON | OFF | OFF | OFF | OFF | OFF | OFF | 1Vdc |

2 | MODE-2 | OFF | OFF | ON | OFF | OFF | OFF | OFF | 2Vdc |

3 | MODE-3 | OFF | OFF | OFF | OFF | ON | OFF | OFF | 3Vdc |

4 | MODE-4 | OFF | OFF | OFF | OFF | OFF | OFF | ON | 4 Vdc |

5 | MODE-5 | ON | OFF | OFF | OFF | OFF | ON | OFF | 5 Vdc |

6 | MODE-6 | OFF | OFF | ON | OFF | OFF | ON | OFF | 6 Vdc |

7 | MODE-7 | OFF | OFF | OFF | OFF | ON | ON | OFF | 7 Vdc |

8 | MODE-8 | ON | OFF | OFF | ON | OFF | ON | OFF | 8 Vdc |

9 | MODE-9 | OFF | OFF | ON | ON | OFF | ON | OFF | 9 Vdc |

10 | MODE-10 | ON | ON | OFF | ON | OFF | ON | OFF | 10 Vdc |

11 | MODE-11 | OFF | OFF | OFF | OFF | OFF | OFF | OFF | 0 |

undergoes high switching frequency to produce multiple output voltage levels. The auxiliary inverter switches s8 to s11 uses fundamental switching frequency. The sample output waveform of the inverter is shown in

Modulation is defined as a technique or methodology to produce the pulses for the semiconductor devices to operate them in ON and OFF states. During on state the device is in saturation region hence the switch starts conducting and during off state the switch is in cutoff region hence the switch stops conducting. Since the width of the pulse computes the width and level of the output voltage it is important to concentrate on the modulation technique. The PWM technique compares the reference and the carrier waveform to produce the switching pulse. The reference will be in line frequency whereas the frequency of carrier decides the switching frequency of the semiconductor device.

The necessary of modulation technique is to produce the switching signals of the semiconductor device such that the output voltage waveform is nearest to the sinusoidal waveform. By achieving the output voltage shape as closest to that of the sinusoidal waveform the lower order harmonics will be reduced which in turn reduces the total harmonic distortion (THD) of the entire system. The modulation methods used in multilevel inverters can be classified according to switching frequency.

Mostly the Multilevel inverter uses the Multicarrier PWM technique to generate switching signals and also the output waveform appears as close as to the sinusoidal one. The multicarrier PWM uses N-1 carriers and the sine wave to produce the switching signals for the N level inverter. It compares the carrier along with the sinusoidal waveform in order to produce the switching signals of the inverter. Depending upon the physical structure of the carrier waveforms they are classified into two types namely:

1) Phase Shifting PWM;

2) Level shifting PWM.

In PS-PWM techniques the carriers are equal in amplitude and frequency but they have phase difference with each other.

In LS-PWM techniques the carriers are equal in amplitude (peak to peak amplitude), same frequency and phase but they differ in their levels of biasing.

There are three alternative PWM strategies with different phase relationships for the level-shifted multicarrier modulation:

・ Phase disposition (PD), where all carrier waveforms are in phase.

・ Phase opposition disposition (POD), where all carrier waveforms above zero reference are in phase and are carrier waveforms below the zero reference are 180 degree out of phase.

・ Alternate phase disposition (APOD), where every carrier waveform both above and below zero reference are in out of phase with its neighboring carrier by 180 degree.

In the present work, in the carrier-based implementation the phase disposition PWM scheme is used. Generally the sinusoidal reference signal is compared with the triangular carriers to produce switching signals to the circuit. In the carrier-based implementation, at every instant of time the modulation signals are compared with the carrier and depending on which is greater, the switching pulses are generated (

Usually for an N-level inverter, the system uses (N − 1) triangular carriers to produce the switching signals. But here our proposed system uses only (N − 1)/2 carriers to produce N level output voltages. Therefore in our system we have not only reduced the number of semiconductor devices but also we have reduced the number of carrier waveform by 50%. Hence the complexity of the control system is reduced which increases the performance of the entire system.

The purpose of controllers is to have a wide range of control over the physical quantities of the system. Especially in industrial applications we use controllers such as speed controller and current controller in order to achieve constant speed and to reduce the harmonic content in the current. In our paper we use proportional Integral controller and Fuzzy Logic Controller to control the speed of the induction motor. Here we also compare the performance of both the controllers.

The Proportional Integral controller uses the Kp and Ki gain to control the system parameter. The proportional gain is used to increases the response of the system but it fails to meet the stability of the system. The Integral is used to have a better stability of the system with reduced speed of response. In general PI controller is used to have fast response with less noise and less disturbance there by reducing the system delays. The basic equation is

where u(t) is the output of the controller, e(t) is the error between the actual and the reference signal, K_{p} is the Proportional gain and K_{i} is the integral gain. He we use trial and error method to find the values of K_{p} and K_{i}. Therefore PI controller ids used to reduce the forced oscillations and steady state error. The structure of PI controller is shown in _{p} and K_{i} are given in

A Fuzzy Logic Controller (FLC) is an extension of a logical system. It works based on the rules called as fuzzy sets. It is basically a rule based system which uses artificial intelligence to frame its fuzzy sets of rules. Fuzzy logic is flexible and it is easy to implement which can tolerate imprecise data and can used to model non linear functions. It comprises of four basic components: Fuzzification, rule-base, inference mechanism and defuzzification (

Gain | Values |
---|---|

Kp | 16.63 |

Ki | 0.016 |

The membership function are assigned to the variables using seven fuzzy subset values called

・ negative big (nb),

・ negative medium (nm),

・ negative small (ns),

・ zero(zr),

・ positive small (ps),

・ positive medium (pm),

・ positive big (pb).

Variable e and ∆e are selected as the input variables, where e is the error and ∆e is the change in error. The output variable is the reference signal for PWM generator which is used to produce the switching signals of the inverter. In our paper we use Triangular membership function for process. Fuzzy associative memory for the proposed system is given in

The proposed model uses only 11 switches and diodes with four asymmetrical voltage sources to 21 levels in the output voltage waveforms. The main inverter produces only positive voltage of levels 1 to 10. The auxiliary inverter converters it positive ten levels, negative ten levels along with one zero level to produce an output of 21 levels at their output voltage.

E | ∆E | ||||||
---|---|---|---|---|---|---|---|

NB | NM | NS | ZR | PS | PM | PB | |

NB | NB | NB | NB | NM | NM | NS | ZR |

NM | NB | NB | NM | NM | NS | ZR | PS |

NS | NB | NM | NM | NS | ZR | PS | PM |

ZR | NM | NM | NS | ZR | PS | PM | PM |

PS | NM | NS | ZR | PS | PM | PM | PB |

PM | NS | ZR | PS | PM | PM | PB | PB |

PB | ZR | PS | PM | PM | PB | PB | PB |

levels zero to −10Vdc. Thus the proposed inverter produces 21 voltage levels with positive and negative levels of +10Vdc to −10Vdc. Here the Vdc used is 25 volts. Hence it is capable of producing amplitude of +250 to −250 volts.

The mathematical modeling of three-phase induction motor is shown in

The output voltage waveform with 21 voltage levels is shown in

S. No | Parameters | Values |
---|---|---|

1 | Stator resistance | 6.03 Ω |

2 | Rotor resistance | 6.085 Ω |

3 | Stator inductance | 489.3e−3H |

4 | Rotor inductance | 489.3e−3H |

5 | Mutual inductance | 450.3e−3H |

6 | Poles | 4 |

induction motor. Hence after 0.5 sec the speed is decreased due to load disturbance. Here the PI controller comes into action and hence the speed is retained after within 0.1 sec and therefore the speed is retained at 0.6 sec and it is maintained at the rated speed.

of the induction motor is increased to 5 N. This results in the increase in speed of the induction motor. Hence after 0.5 sec the speed is decreased due to load disturbance. Here the PI controller comes into action and hence the speed is retained after within 0.07 sec and therefore the speed is retained at 0.57 sec and it is maintained at the rated speed.

The proposed asymmetric cascaded multilevel inverter produces multilevel output with minimum number of power semiconductor devices. The LS-PD-PWM technique involved to further improve the performance of the inverter by reduces the THD which was illustrated in the comparison tables. The simulation also proves that if any failure

PI | FUZZY | |
---|---|---|

Rise time (sec) | 1.3 | 1.3 |

Settling time (sec) | 0.1 | 0.07 |

Overshoot time (sec) | 0.4 | 0.2 |

MC-PD-LS-PWM | PI | FUZZY | |
---|---|---|---|

Total harmonic distortion | 10.08 | 5.50 | 2.36 |

occurs in any one of the switches it is still capable of producing multiple voltage levels without shunt downing the entire systems. The multilevel inverter was successfully controlled by both PI and fuzzy logic controller and these were used to achieve control of multilevel output steps both in linear and nonlinear loads. From

Namith, A.A. and Sivakumaran, T.S. (2016) A Novel Asymmetric Three-Phase Cascaded 21 Level In- verter Fed Induction Motor Using Multicarrier PWM with PI and Fuzzy Controller. Circuits and Systems, 7, 3922-3950. http://dx.doi.org/10.4236/cs.2016.711327