This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important feature s . When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aim s at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.
Power consumption is a major problem while designing VLSI circuit. Few technologies were adapted to reduce the power consumption while designing VLSI circuit. One of the technologies is CMOS. Network routers which are used for the packet data transmission, go through the process of IP address matching technique. The matching technique requires the lookup table which has the problem of multiple data access. The new idea of content addressable memory (CAM) is the most popular hardware solution to support the high lookup table speed. The CAM is address by data rather than by address. Since search can be done in parallel, it leads to faster data search than the software lookup. The CAM is widely used in Translation Look aside Buffer (TLB), high associative cache, image processing, database and network routers, etc.; all require fast table lookup.
The routers used in the network applications demand a high speed TCAMs for packet filtering. The TCAM provides the fast look-up table for data and address routing. The network router uses the TCAM and SRAM cell which is used to provide the high speed searching and data storage capacity. However on the fabricating side of TCAM it occupies a large silicon area space. It also creates the problem of stability. Since it occupies a huge area comparatively the power consumption of the TCAM increases drastically. There is a huge power-dissipation problem because of the search operation which is carried out parallel in a chip which is of large size. Just because of the large power dissipation the reliability of the chip is questioned and this again leads to the problem of increase in the package cost of the IC. There were many works reported on the attempt of reducing the power dissipation but that failed to solve the problem of area overhead and noise immunity. Another important problem is the reduction in the yield.
Because of these problems, it attributes to the following shortcomings: 1) increase in chip size, 2) increase in power dissipation, and 3) reduction in the yield, which lead to a production cost overhead. They have to be solved to realize cost-efficient large-scale TCAM chips.
For power consumption, a TCAM consumes power mainly in 3 parts: clock and control, match line, and search line (SL). Thanks to the advancement of match-line design techniques, the power consumption of the former has been greatly reduced. This can be seen from the works of the past three years [
As discussed in [
In contrast, this paper introduces a low-power TCAM design that consists of two newly developed schemes, i.e., the refined search enable (RSE) and “don’t care” gating (DCG) schemes. Without any performance penalty and complex control circuitry, our design can largely reduce the TCAM power dissipated in the SLs by minimizing both the SL switching activity and the average power consumption per SL switch.
In this paper, we propose a novel Data Aware TCAM (DATCAM) cell which consists of improved Search Enable Line (SEL) and Data Aware Intelligent “Don’t Care” Gating (DAIDCG) to solve the problems of power consumptions. The proposed architectures are attractive for realizing small chip size, low-power and high-throughput operation. In addition the architecture has a great impact on the yield improvement. A 4.5-Mb DATCAM design verifies these advances quantitatively.
Data aware proposed TCAM cell is shown in
The back to back connected inverted store the value. The simulated lines for different signal are shown in
In order to gate the search data from being broadcast over the entire SL, our design inserts the GNs to break the entire SL into several segments. As shown in
There are four possible ways of subsequent data transmission, it may have “1” followed by “0” or “1” similarly “0” followed by “0” or “1” but among the above possibilities the transition which move from “0” to “1” or “1” to “0” will cause the node capacitor to charge and discharge which leads to power consumption. In addition, the Data correlation block will look after the inter signal dependencies that exist between two signals and finally the data computation/comparison is done based on the signal dependencies. In the conventional TCAM with differential SL scheme [
Search Data | Case A: Without SC | Case B: With SC | ||
---|---|---|---|---|
S | S Bar | S | S Bar | |
0 | 0 | 1 | 0 | 1 |
0 | 0 | |||
0 | 0 | 1 | 0 | 1 |
0 | 0 | |||
0 | 0 | 1 | 0 | 1 |
0 | 0 | |||
0 | 0 | 1 | 0 | 1 |
0 | 0 | |||
0 | 0 | 1 | 0 | 1 |
N0→1 = 4 | N0→1 = 0 |
A straightforward solution to this short comings is the introduction of an additional transistor that is used to disconnect the pull-down path during the ML pre-charge, and then enable the search operation during the evaluation phase. This concept is referred to as ISEL scheme, and it is illustrated in
In the traditional TCAM if the cell is matched in the evaluation phase, then the pull-down path is conducted, whose length is three transistors, i.e., N1, N2, and N3. The number of transistor in the critical path is high for A in the worst case, in which only one TCAM cell is matched, the increased path would lengthen the time to discharge the ML to 0. Thus, the search performance degradation is inevitable. In order to eliminate the aforementioned performance penalty, the pull-down logic of TCAM cell is refined, as illustrated in
result in such that N2 is OFF, and N4 is ON. Thus, node Z follows the XOR result to control N1. The ML is discharged to 0 only when S is not equal to D. Since the length of the conducted pull-down path (P1) is 2, the proposed design can achieve the same search performances the conventional TCAM design without the SE scheme.
In
The circuits are designed with an intention of making the circuit intelligent enough to detect the computation based on the signal correlation and also it tries to reduce the unnecessary switching in the circuits. This subsequently reduces the power consumption of the circuits. The circuits are constructed using virtuoso of cadence and simulated using the spectre. The circuits were simulated using the model file of 90 nm from
Work | Technology (nm) | Voltage (v) | Search time (ns) | Energy (fJ)/search/bit |
---|---|---|---|---|
Jinn Shyan et al. | 130 | 1.2 | 1.10 | 0.35 |
Igor Arsovski et al. | 130 | 1.2 | 1.40 | 2 |
Conventional | 180 | 1.8 | 3.04 | 3.7 |
This work | 90 | 1 | 0.82 | 0.16 |
Design | Energy | |
---|---|---|
Quite pattern | Switch pattern | |
(0 - >0/1 - >1) | (0 - >1/1 - >0) | |
Conventional | 6.34E−05 | 6.35E−05 |
This work | 4.05E−05 | 5.20E−0.5 |
TSMC library. The Verilog simulated in the Modelsim is used in the digital porion of the study design. The results are compared with the previous work in this domain.
For accurate evaluation, we use the TSMC 0.18-CMOS technology to layout three IPv4 routing tables, and all data are obtained from the post layout simulation. The table size is fixed at 128 * 32, i.e., 128 entries by 32 bits, for all tables.
This paper tries to develop a data aware AND-type match line architecture and complexity less improved search line architecture for TCAM. The proposed architecture in search line tries to explore the feasibility of power reduction in the search line by exploiting the inter- and intra-data dependencies. A TCAM Marco of 256 × 128 b was designed using Cadence ADE with 90 nm technology file from TSMC. The simulated results show that the proposed data aware architecture provides around 40% reduction in search time and 55% reduction in the energy consumption over the existing architecture.
Mathan, K. and Ravichandran, T. (2016) Data Intelligent Low Power High Performance TCAM for IP-Address Lookup Table. Circuits and Sys- tems, 7, 3734-3745. http://dx.doi.org/10.4236/cs.2016.711313