This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephthalate (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic transistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of polymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (V T), subthreshold slope (S), mobility ( μ), onset voltage (V on) and I on/I off ratio have been studied. The results showed that the recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the transistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift associated to charge trapping, while keeping the μ, I off current and S minimally affected. Regardless of whether Device 2 exhibited better electrical performances and stability in ON state, we observed a bias stress-induced increase of depletion current and subthreshold slope in subthreshold region, a sign of defect creation. Both devices showed onset voltage shift in opposite direction.
Organic semiconductors have enabled the emergence of new exciting research field called organic electronics. This enthusiasm for devices based on organic materials is partly driven by the increased interest in both academic and industry thanks to a low manufacturing cost, mass production, compatibility with flexible substrates compared to their equivalent inorganic materials. Transistor remains unambiguously a key element of electronics devices and is especially present in most new technologies. The considerable development of organic field effect transistors (OFETs)―in which the active layer is organic semiconductor, enables to foresee applications in fields such as flat display driving, radio frequency identification (RFID) tag and sensors [
Many interesting techniques had been used for fabrication of organic transistor devices, and each of them showed advantages and disadvantages. Although organic semiconductor can be processed on flexible substrate they generally do not withstand conventional lithography techniques. This gives rise the development of alternative deposition and patterning methods leading to the concept of soft lithography which is introduced in the end of the 1990s [
However, a major drawback of OFETs is the lack of stability making them a critical issue that must be addressed before their commercialization. Hysteresis is an instability that can be frequently observed during device operation. It appears as a difference in the source-drain current values observed during forward and backward scans of the gate or drain voltages. Therefore, minimizing the hysteresis effect is a priority in electronic circuits.
It was also reported that a prolonged polarization of gate electrode named bias stress tends to shift the threshold voltage, degrades the subthreshold parameters [
In this paper, we report on electrical instabilities in pentacene-based transistors with Mylar and PMMA/Mylar gate dielectrics transferred by a lamination process in ambient environment. Special emphasis is given on comparing the two types of devices in ON state and subthreshold regions under gate bias stress. Device with PMMA/Mylar dielectric exhibited good performances and stability in ON state, while in depletion regime, the subthreshold parameters were degraded. In contrast, the device using only Mylar as dielectric has an opposite behavior. In addition, both devices showed onset voltage shifts in opposite direction.
The substrate was a 175 nm thick PET foil (DuPont Melinex ST 504) thoroughly sonically cleaned. The different transistor fabrication steps are described in
After pressure release, a 70 nm pentacene film is evaporated onto the Mylar foil at a substrate temperature and a deposition rate of 70˚C and 0.02 nm/respectively. The device is completed by the deposition of Au source and drain electrodes through a shadow mask. The channel width and length were, respectively, 2 mm and 50 µm. Device 2 is different to Device 1 by spin coating 80 nm thick PMMA layer on the top of the transferred Mylar foil. PMMA was annealed in air for 20 min at 120˚C. Pentacene was then deposited on PMMA followed by the evaporation of top Au source and drain contacts. PMMA is also expected to slightly planarize the Mylar surface and thus lead to a smoother surface. The process flow Mylar lamination for transistors fabrication is represented in
where ID,sat is drain current in the saturation regime; W/L is the width to length ratio; C is the capacitance per unit area; VG the gate voltage and VT the threshold voltage.
The morphology of the pentacene thin films was studied in an Amplitude Modulation mode Atomic Force Microscopy (AM-AFM) using the AFM Solver P-7, “stand alone” Smena-B (NT-MDT, Russia), with typical spring constant k of 22 N/m and tip radius of 10 nm. This mode was shown to be more appropriate than the contact mode to image soft materials such as polymers, functionalized surface and biological objects, in air.
Bottom-Gate/Top-Contact (BG/TC) thin-film transistors were fabricated as described in the experimental part. All measurements were performed in air at room temperature and in the dark. For all two devices, the organic transistors operate in the accumulation mode since the gate electrode is biased negatively with respect to the grounded source electrode. Drain current (ID) is almost linear with drain voltage at low VD, whereas it tends to saturate at higher drain voltage due to the pinch off of the accumulation layer.
To study the electrical instability related to hysteresis, we performed electrical measurements in forward and back scans. As we can see, Device 1 exhibits a hysteresis in forward and reverse characteristics (
To better understand this difference, AFM images were performed in order to identify the morphology of pentacene layer that can explain the relation between they nanostructures and the charges carriers mobility.
Devices | VT (V) | μ (cm2∙V−1∙s−1) | Ion/Ioff | S (V/decade) |
---|---|---|---|---|
Device 1 | −25 | 4.1 × 10−3 | 1.3 × 102 | 19 |
Device 2 | −20 | 5.3 × 10−2 | 5 × 103 | 8 |
the combination of these two effects leads to electrical parameters degradation [
In contrast, thanks to the PMMA layer, Device 2 exhibits improved performances.
To study the bias stress-induced degradation in transistor devices, a constant gate voltage was applied to the organic transistors. To determine the changes in the transfer curves, the applied gate voltage is interrupted at short time intervals by a sweep of the gate. This technique allowed us to obtain the electrical parameters.
part of the curve, which is proportional to the field effect mobility in the saturation regime, is similar for all curves. The extracted mobility remains minimally affected after the application of gate bias stress (−50 V/3000 s).
The negative threshold voltage shift associated to negative gate bias is a consequence of holes being trapped.
Regarding the transistor with PMMA/Mylar as dielectric, both mobility and threshold voltage remain unchanged after negative bias stress of −50 V for 3000 s as it was operating in ON state (
The grain boundaries play a crucial role in the bias stress effect [
These latter are synonyms of traps, a prolonged polarization of the gate electrode permanently creates a constant electric field, which promotes a continuous charge trapping. However, the large grain sizes (less grain boundaries) on PMMA/Mylar reduce the number of traps, accordingly, the charge trappings decrease.
Another key parameter that must be addressed is the onset voltage Von which is critically influenced by the semiconductor/dielectric interface. The onset voltage is determined as the minimum of the drain courant versus gate voltage in logarithmic scale and it is highly desirable to get a near-zero Von in circuitry. After bias stress the onset voltage of Device 2 is shifted towards positive gate values with ∆Von = +15 V, while for Device 1 it is negatively shifted and ∆Von = −10 V after 3000 s under bias stress, showing an opposite behavior. The onset voltage shift of Device 1 is exactly similar to the threshold voltage shift ∆Von = ∆VT = −10 V. According to Knipp et al. [
Electrical performances and instabilities of transistors based on pentacene semiconductor with laminated Mylar and PMMA/Mylar dielectrics have been studied. Hysteresis has been observed with the device using only Mylar as dielectric. In contrast, no hysteresis has been recorded for the device using PMMA/Mylar double layer. Hysteresis apparition was related to the pentacene grain sizes; the large gain of pentacene obtained with PMMA prevent any moisture diffusion compared to pentacene growth on Mylar showing small grain sizes and more grain boundaries. These latter are considered as an ideal environment for charge trapping. Negative bias stress performed in ambient air leads to electrical parameters degradation depending on operating regimes. In ON state the transistor with Mylar exhibited a high threshold voltage shift with a minimal change of mobility and Ion/Ioff ratio after bias stress. However, the transistor using PMMA/Mylar showed good electrical performances in ON state but in subthreshold regime, the depletion current increased as well as the subthreshold swing due to the doping and bias-assisted moisture/oxygen diffusion leading to defect creation. Both devices showed onset voltage shift in opposite direction. Mylar lamination is a powerful technique for transistor fabrication whether in bottom or top gate configurations for mass fabrication in ambient environment. Our research is in progress to optimize the electrical parameters especially by improving the dielectric lamination and to understand the complex bias stress phenomenon that remains so far poorly understood in order to minimize the transistor instability.
A. K. D acknowledges the FIRST (Fonds d’Impulsion pour la Recherche Scientifique et Technique) program for financial support.
Abdou Karim Diallo,Abdoul Kadri Diallo,Diouma Kobor,Marcel Pasquinelli, (2016) Electrical Instability in Pentacene Transistors with Mylar and PMMA/Mylar Gate Dielectrics Transferred by Lamination Process. Journal of Applied Mathematics and Physics,04,1202-1209. doi: 10.4236/jamp.2016.47125