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This paper presents a new transformer based multilevel inverter, with a novel pulse width modulation scheme to achieve seven-level inverter output voltage. The proposed inverter switching pattern consists of three fundamental frequency sinusoidal reference signals with an offset value, and one high frequency triangular carrier signal. This switching scheme has been implemented using an 8-bit Xilinx SPARTAN-3E field programmable gate array based controller. In addition, the state space model of the proposed inverter is developed. The significant features of the proposed topology are: reduction of the power switch count and the gate drive power supply unit, the provision of a galvanic isolation between load and sources by a centre tap transformer. An exhaustive comparison has been made of the existing multilevel inverter topologies and the proposed topology. The performances of the proposed topology with resistive, resistive-inductive loads are simulated in a MATLAB environment and validated experimentally on a laboratory prototype.

Recently, multilevel inverters have been receiving increasing attention, because of their many features: it has higher voltage operating capability, reduced rate of change of voltage (dv/dt), lower common mode voltages, reduced harmonic content, near sinusoidal voltage and current, smaller output filter. Multilevel inverters are considered as one of the industrial solutions for high dynamic performance and power quality demanding applications [

In [^{n} level of output voltage and the turns ratio of the secondary winding of the transformer plays a role to generate n-level of the output voltage, consequently making the system bulky in size and expensive. A single source cascaded transformers reduced switch multilevel inverter (CTRSI) has been presented in [^{n} level of output voltage, but can generate any level of output voltage. But the major drawbacks of this topology are the requirement of more number of power switches and transformers on the output side, which will increase the volume of the system and cost. A transformer based symmetrical and asymmetrical cascaded multilevel inverter has been proposed in [

The present work focuses on transformer based new multilevel inverter topology, which is composed of three isolated DC voltage sources, five power switches and one single phase centre tap transformer to generate seven- level output voltage. The inverter structure uses a novel pulse width modulation (PWM) switching pattern to produce controlled output voltage. The proposed topology has salient inherent features such as a galvanic isolation between an input dc source and output load, which enhance the reliability of the inverter. This topology can be recommended for power conditioning devices and renewable energy power generation systems. A computer aided simulation and experimental results are used to justify the proposed topology and to show the validity of the presented inverter structure for real time applications.

This paper is organized as follows: Section 2 presents the structure and details of the mode of operation of the proposed inverter, with mathematical formulations. Section 3 describes the novel switching scheme for the proposed inverter. Section 4 presents the state space model of the proposed topology. Section 5 discusses the simulation and experimental results of the proposed inverter. Section 6 presents the comparison of the proposed topology with the classical and recent topologies. Finally, Section 7 concludes the paper based on the simulation and experimental results.

The proposed single-phase seven-level inverter comprises three equal value of dc sources, five unidirectional power switches, and a centre tap transformer as shown in

For symmetrical mode of operation_{dc}, 2V_{dc}, 3V_{dc}, 0, −V_{dc}, −2V_{dc}, −3V_{dc} from the constant input dc voltage sources. The switches S_{1}, S_{2} and S_{3} determine the level of the output voltage, and the switches S_{4} and S_{5} decide the polarity of the output voltage. The number of output voltage levels (N_{STEP}), the required number of IGBTs (N_{IGBT}), for the proposed topology is computed from the following equations.

where, N_{s} is the number of sources. Here, the number of sources decides the output voltage level.

_{4} and S_{5} are operating in the fundamental frequency, and the other switches are operating at 1 kHz. This indicates that the proposed inverter has a reduction in conduction and switching losses, which results in an increase in the effi- ciency of the proposed inverter. To understand the operation of the proposed inverter, the following modes are

explained using seven switching states, as shown in Figures 3(a)-(g). Here, the red line represents the conduction path of the current flow. The required seven levels of output voltage are generated as follows.

・ Mode 1: Output Voltage of

_{3} and S_{4} are kept ON, three sources (V_{dc}_{1}, V_{dc}_{2} and V_{dc}_{3}) are connected in series, and supply energy to the load. The load current flows from the terminal a to b and the voltage across the load terminals are +3V_{dc}.

・ Mode 2: Output Voltage of

_{2} and S_{4} are kept ON, two sources (V_{dc}_{2} and V_{dc}_{3}) are connected in series and supply energy to the load. The load current flows from terminal a to b and the voltage across the load terminals are +2V_{dc}.

・ Mode 3: Output Voltage of (+V_{dc}_{3})

_{dc}_{3}. When switches S_{1} and S_{4} are kept ON, source (V_{dc}_{3}) supplies energy to the load. The load current flows from terminal a to b, and the voltage across the load terminals are +V_{dc}.

・ Mode 4: Zero Output Voltage (0)

_{5} and body diode of S_{4} is ON and all other controlled switches OFF. The primary winding of the centre tap transformer is short circuited, and the voltage applied to the load is zero.

・ Mode 5: Output Voltage of (−V_{dc}_{3})

_{dc}_{3}. When switches S_{1} and S_{5} are kept ON, source (V_{dc}_{3}) supplies energy to the load. The load current flows from terminal b to a and the voltage across the load are −V_{dc}.

・ Mode 6: Output Voltage of

_{2} and S_{5} are kept ON, the two source of _{dc}.

・ Mode 7: Output Voltage of

_{3} and S_{5} are kept ON, three source of _{dc}.

The mathematical formulation for the proposed inverter is as follows: Let B_{j} be a switching function corresponding to switch S_{j} (j = 1 to n) defined as [

The inverter output voltage

where

The following equations give the instantaneous inverter output voltage and current of the proposed inverter,

The proposed switching scheme utilizes fundamental frequency (50 Hz) of three unidirectional sinusoidal waves as reference signal with offset voltage, and one triangular carrier signal of 1 kHz. The reference signals have the same amplitude and frequency and are in phase with an offset value that is equivalent to the amplitude of the carrier signal. By comparing each reference signal with a carrier signal, a control signal is produced for switching a device in the proposed MLI.

_{4} is derived by comparing reference signal (V_{ref1}) with zero and S_{5} is obtained from inverting signal of S_{4}. The pulse pattern for S_{1} is arrived by comparing V_{ref1}, V_{ref2} with V_{carrier} and the pulse pattern for S_{2} is derived by comparing V_{ref2}, V_{ref3} with V_{carrier}. Similarly, the pulse pattern for S_{3} is arrived by comparing V_{ref3} with V_{carrier}. Here, it is seen that, the level modulated switches S_{1}, S_{2}, S_{3} operate at switching frequency of 1 KHz (carrier frequency) and polarity modulated switches S_{4} and S_{5} operate at fundamental frequency (reference frequency) of 50Hz. The switching interval for the seven-level inverter is represented by seven modes as follows:

Mode 1:

Mode 2:

Mode 3:

Mode 4:

Mode 5:

Mode 6:

Mode 7:

According to the amplitude of the reference signal, the operational interval of each mode varies within a definite period. The angles

Switching State of each Power Device | Inverter Output Voltage Level in volts (V_{o}) | ||||
---|---|---|---|---|---|

S_{1} | S_{2} | S_{3} | S_{4} | S_{5} | |

OFF | OFF | ON | ON | OFF | +V_{dc} |

OFF | ON | OFF | ON | OFF | +2V_{dc}/3 |

ON | OFF | OFF | ON | OFF | +V_{dc}/3 |

OFF | OFF | OFF | OFF | ON | 0 |

ON | OFF | OFF | OFF | ON | −V_{dc}/3 |

OFF | ON | OFF | OFF | ON | −2V_{dc}/3 |

OFF | OFF | ON | OFF | ON | −V_{dc} |

about the output voltage according to the switching state of the ON/OFF condition.

The amplitude modulation (M_{a}) of the proposed seven-level inverter can be calculated as follows,

where V_{ref} is the amplitude of the sinusoidal signal, and V_{carrier} is the amplitude of the triangular signal. The level of the inverter output voltage changes with the modulation index.

(9)

The Equation (9) gives the information about the level of the inverter based on the value of the modulation index (M_{a}).

A state space model of a system consists of state equation and output equation. The state equation of a system is a function of state variables and inputs as defined by Equation (10). The state equation is a set of variables which describes the system at any instant of time. The output equation of the system is a function of state variables and outputs defined by Equation (11). The state space representation provides a convenient way to model and analyze the many input many output (MIMO) systems. The state model of the system defined as [

The output voltage of the inverter circuit is the secondary voltage across the load. To facilitate the analysis of the circuit, the secondary impedance and the load impedance are referred to the primary winding as shown in

where,

Control signal,

The state variable of the circuit are the source current i_{s}, the magnetizing current i_{m} and the output current i_{o}. Equations (12), (13), (14) are rewritten as,

Substitute Equation (20) into Equations (19) and (21)

From Equations (20), (22) and (23) the state space model of the inverter circuit is formulated as,

Equation (24) gives the state equation of the proposed inverter. Division of the Equation (24) by the fundamental frequency, result in normalized state equation of the system.

where

The simulation and experimental hardware results are presented to verify the validation of the proposed transformer based multilevel inverter. A computer-aided simulation has been carried out to validate the performance of proposed seven-level inverter with R and R-L Load using MATLAB/Simulink environment.

To validate the proposed topology, a prototype of the single phase seven-level inverter is developed in the laboratory. The photograph of the setup is shown in

TLP250) circuits. The generation of PWM waveform for the proposed inverter through Xilinx is shown in

_{1}, S_{2}, S_{3}) are operated at a high frequency and polarity changed switches (S_{4}, S_{5}) are operated at a fundamental frequency.

To make clear the understanding of the evolution of the transformer based multilevel inverter structures are presented in

Another decisive factor to assess the performance of the multilevel inverters is the number of on-state switches.

structure presented in [

In this paper, a prototype model of transformer based seven-level inverter has been implemented with a novel

PWM switching technique using FPGA controller. The state space model of the proposed inverter has been developed. The proposed multilevel inverter utilizes five power switches and one centre tap transformer to generate seven-level output voltage. The working nature of the proposed topology, mathematical formulation and a novel PWM technique have been analyzed in detail. This work has been compared with the classical and recent MLIs. Based on the comparative study, it is confirmed that the proposed MLI utilized the minimum number of switching devices with gate drive circuits, and the on-state switches through the current path are also reduced. In

Components | Conventional CHBMLI | Proposed in [ | Proposed in [ | Proposed in [ | Proposed Topology |
---|---|---|---|---|---|

Number of Power Switches | |||||

Number of Gate Drivers | |||||

Number of on-state Switches | 2 | ||||

Number of transformers | - | 1 |

Components | Conventional CHBMLI | Proposed in [ | Proposed in [ | Proposed in [ | Proposed Topology |
---|---|---|---|---|---|

Number of Power Switches | 12 | 8 | 12 | 6 | 5 |

Number of Gate Drivers | 12 | 8 | 8 | 6 | 5 |

Number of on-state Switches | 6 | 6 | 6 | 3 | 2 |

Number of transformers | - | 3 | 4 | 1 | 1 |

order to validate the operation and performance of the proposed inverter, the MATLAB simulation and the experimental prototype model are developed and tested with unity and a lagging power factor loads.

R. Gandhi Raj,S. Palani,H. Habeebullah Sait, (2016) State Space Modeling and Implementation of a New Transformer Based Multilevel Inverter Topology with Reduced Switch Count. Circuits and Systems,07,446-463. doi: 10.4236/cs.2016.74038