^{*}

^{*}

^{*}

^{*}

^{*}

In this paper, a simple control algorithm for the dynamic voltage restorer (DVR) is proposed to mitigate the power quality problems in terminal voltage such as sag, swell, harmonics, unbalance etc. Two PI (proportional-integral) controllers are used each to regulate the dc bus voltage of DVR and the load terminal voltage respectively. The fundamental component of the terminal voltage is extracted using the synchronous reference frame theory. The control signal for the series connected DVR is obtained indirectly from the extracted reference load terminal voltage. The proposed DVR control strategy is validated through extensive simulation studies using MATLAB software with its Simulink and Sim-power system (SPS) block set tool boxes.

Power quality issues in the distribution system are widely addressed in the literature [1-9] due to the sensitive and critical loads such as precise manufacturing plants, automation etc. A new group of devices based on PWM (Pulse Width Modulated) switching solid state compensators are developed and used for improving power quality in the distribution system under the generic name of custom power devices [3,7]. They are mainly of three categories such as shunt connected distribution static compensator (DSTATCOM), series connected compensator like dynamic voltage restorer (DVR) and unified power quality conditioner (UPQC) which is connected in both shunt and series with the ac mains. The series connected compensator can regulate the load terminal voltage from the “low quality” terminal voltage and protect the critical consumer loads from tripping and consequent loss. The installation of custom power devices at the consumer point is governed by the IEEE standard [

A DVR is connected between the supply and the sensitive load so that it can inject a voltage of required waveform. Hence it can protect sensitive consumer loads from supply disturbances. In a capacitor supported DVRthe power absorbed/supplied is almost zero except small losses in the steady state and the voltage injected by the DVR should be in quadrature with the feeder current [

The SRFT (synchronous reference frame theory) based algorithm reported in [

The schematic diagram of a capacitor supported DVR is shown in _{sa}, v_{sb}, v_{sc}) represent a 3-phase three-wire supply system and the series source impedances are shown as Z_{a} (L_{a}, R_{a}), Z_{b} (L_{b}, R_{b}) and Z_{c} (L_{c}, R_{c}). The DVR uses a transformer (T_{r}) to inject a voltage in series with the terminal voltage. A voltage source converter (VSC) along with a dc capacitor (C_{dc}) is used as a DVR. The ripple in the injected voltage is filtered using a series inductor (L_{r}) and a parallel capacitor (C_{r}). The load considered is a three phase lagging power factor load.

The ripple filter is designed based on the switching frequency (f_{s}). It is designed such that the capacitor (C_{r}) offers a low impedance path for the switching ripple and the series inductor (L_{r}) provides high impedance for the switching ripple. The reactance given by the capacitor (C_{r}) and inductor (L_{r}) at half of the switching frequency (5 kHz) for f_{s} = 10 kHz i.e., f_{r} = f_{s}/2 is calculated as

X_{Cr} = 1/(2*π* f_{r} *C_{r}) = 1/(2*3.14*5000*C_{r})(1)

X_{Lr} = 2*π* f_{r} *L_{r} = 2*3.14*5000*L_{r}.(2)

Considering, X_{Cr} = 3 Ω, C_{r} = 10.61 μF and X_{Lr} = 100 Ω, L_{r} = 3.18 mH. These values of ripple filter elements are initially used for simulation and by iteration it is found that, L_{r}= 3.5 mH and C_{r} = 10 μF are suitable for minimum ripple in the output of DVR.

_{L}_{(presag) }and I_{L}’. After the sag event, the terminal voltage (V_{t}) is of lower in magnitude that of pre-sag condition. The voltage injected by the DVR (V_{c}) is used to maintain the load voltage (V_{L}) at the rated magnitude and this has two components, V_{cd} and V_{cq}. The voltage in-phase with the current (V_{cd}) is to regulate the dc bus voltage of DVR and also to meet the power loss in the DVR. The voltage in quadrature with the current (V_{cq}) is to regulate the load voltage (V_{L}) at constant magnitude. The aim of the control algorithm is to achieve these two components of the injection voltage. The sag, swell, harmonic and unbalance in terminal voltage are also compensated by the proposed DVR through extracting the required reference load voltage.

The proposed control algorithm is derived from the algorithm presented in [

The reference load terminal voltages (, ,) are derived from the sensed supply currents (i_{Sa}, i_{Sb}, i_{Sc}), terminal voltages (v_{ta}, v_{tb}, v_{tc}) and the dc bus voltage (v_{dc}) of DVR as feedback signals. There are two proportionalintegral (PI) controllers used to regulate the dc bus voltage of DVR and to regulate the load voltage (v_{L}).

Three phase in-phase unit voltage templates (u_{a}, u_{b}, u_{c}) are derived from the supply currents (i_{Sa}, i_{Sb}, i_{Sc}) as,

u_{a} = i_{sa}/i_{T}; u_{b} = i_{sb}/i_{T}; u_{c} = i_{sc}/i_{T}; (4)

Moreover, the quadrature unit vectors (x_{a}, x_{b}, x_{c}) are derived from the in-phase unit vectors as,

The dc bus voltage of the DVR is regulated using a PI controller over the sensed (v_{dc}) and reference values () of dc bus voltage. This PI controller output is considered as the amplitude () of the in-phase component of the injection voltages (^{*}, ,) as,

A second PI controller is used to derive the amplitude () of the quadrature component of the injection voltages (, ,) of the DVR by using it over the amplitude of sensed load voltage (V_{Lp}) and reference value () of the load terminal voltage as,

To estimate the positive sequence fundamental component of terminal voltages (v_{ta}_{1}, v_{tb}_{1}, v_{tc}_{1}), the sensed terminal voltages (v_{ta}, v_{tb}, v_{tc}) are required. Two phase unit voltage vectors are derived using a PLL (phase locked loop) over the terminal voltage. The fundamental component of the terminal voltages (v_{ta}_{1}, v_{tb}_{1}, v_{tc}_{1}) are extracted from the sensed terminal voltages (v_{ta}, v_{tb}, v_{tc}) using the synchronous reference frame (SRF) transformation [

The algebraic sum of the in-phase components (, ,), the quadrature components (, ,) and the fundamental of terminal voltages (v_{ta}_{1}, v_{tb}_{1}, v_{tc}_{1}) are taken as the reference load voltages (, ,) as,

A pulse width modulated (PWM) controller is used over the reference (, ,) and sensed load voltages (v_{La}, v_{Lb}, v_{Lc}) to generate gating signals for the IGBT’s (Insulated Gate Bipolar Transistors) of the DVR. The carrier wave (triangular) frequency is set at 10 kHz. The gating pulses switch the IGBT’s of the DVR for the compensation of sag, swell, unbalance and harmonics in terminal voltage.

The control algorithm for the DVR is modeled in MATLAB and is given in

voltages to generate gating signals for the IGBT’s (Insulated Gate Bipolar Transistors) of the DVR.

The performances of the DVR for different supply disturbances are tested under various operating conditions. The proposed control algorithm is tested for different power quality events like voltage sag (_{c}) in series with the terminal voltage (v_{t}). The load voltage (v_{L}) is regulated at the rated value. The supply current (i_{s}), amplitude of terminal voltage (V_{Sp}), the amplitude of load voltage (V_{Lp}) and the dc bus voltage (v_{dc}) are also shown in

The dynamic performance of the DVR for a swell in terminal voltage is given in _{L}) is regulated at rated value, which shows the satisfactory performance of the DVR. The supply current (i_{s}), the amplitude of load voltage (V_{Lp}), the amplitude of terminal voltage (V_{tp}) and the dc bus voltage (v_{dc}) are also shown in the

the reference value, though small fluctuations occur during transients.

The performance of DVR for an unbalance in terminal voltages is shown in _{t}) of _{c}) so that the load voltage (v_{L}) is regulated to constant magnitude. The supply current (i_{s}), the amplitude of load voltage (V_{Lp}), the amplitude of terminal voltage (V_{tp}) and the dc bus voltage (v_{dc}) are also shown in

The harmonics compensation in terminal voltage is tested and depicted in _{t}) is distorted and the load voltage (v_{L}) is undistorted and constant in magnitude due to the injection of harmonic voltage (v_{c}) by the DVR. The load terminal voltage (v_{L}) has a total harmonic distortion (THD) of 1.2% (

A new control algorithm based on proportional-integral controllers has been proposed for a capacitor supported dynamic voltage restorer. The proposed algorithm is based on the estimation of in-phase and quadrature component of injection voltages using two PI controllers each for regulating the dc bus voltage of DVR and the load voltage respectively. The reference voltages for the DVR have been obtained indirectly by extracting the reference load terminal voltage. The proposed control algorithm of

DVR has been validated through simulation using MATLAB software along with simulink and Simpower system (SPS) toolboxes. The performance of the DVR has been observed to be satisfactory for various power quality disturbances like sag, swell, unbalance and harmonics in PCC voltages. Moreover, it is able to provide a self-supported dc bus of the DVR through power transfer from ac line at fundamental frequency.

Parameters of the DVR connected system Line Impedance: L_{s}= 3.5 mH, R_{s}= 0.01 Ω

Load: 8.5 kVA, 0.707 pf Lag.

Ripple filter: C_{r} = 1 µF, L_{r} = 3.1 mH.

DVR:

DC bus voltage: V_{dc} = 150 V.

DC bus capacitance: C_{dc} = 1000 µF.

AC line voltage: V_{LL} = 415 V, 50 Hz.

DC bus PI Controller: K_{p}_{1} = 0.1, K_{i}_{1 }= 1.

AC terminal voltage PI Controller: K_{p}_{2} = 0.21, K_{i}_{2} = 2.2.

PWM switching frequency: 10 kHz.

Transformer: 10 kVA, 100 V/400 V