This paper presents the design and implementation of a low-pass, high-pass and a hand-pass Finite Impulse Response (FIR) Filter using SPARTAN-6 Field Programmable Gate Array (FPGA) device. The filter performance is tested using Filter Design and Analysis (FDA) and FIR tools from Mathworks. The FDA Tool is used to define the filter order and coefficients, and the FIR tool is used for Simulink simulation. The FPGA implementation is carried out using Spartan-6 LX75T-3FGG676C for different filter specifications and simulated with the help of Xilinx ISE (Integrated Software Environment). System Generator ISE design suit 14.6i is used in synthesizing and co-simulation for FPGA filter output verification. Finally, comparison is done between the results obtained from the software simulations and those from FPGA using hardware co-simulation. The simulation waveforms and synthesis reports verify the parallel implementation of FPGA which proves its effectiveness in terms of speed, resource usage and power consumption.
In signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range [
An ideal filter is a network that allows signals of only certain frequencies to pass while blocking all others. Depending on the region of frequencies that are allowed through or not, filters are characterized as low-pass, high-pass, band-pass, band-reject and all-pass. There are many needs for electric filters, some of the more common being those used in radio and television sets, which allow tuning into a certain channel by passing its band of frequencies while filtering out those of other channels [
The FIR filters are widely used in signal processing and can be implemented using programmable digital processors. Due to the high performance requirements and increasing complexity of DSP and multimedia communication applications, filters with a large number of taps are required to increase the performance in terms of high sampling rate. As a result, the filtering operations are computationally intensive and more complex in terms of hardware requirements [
In order to reduce the cost, time-to-market has to be shortened, the price of a controller device has to be cheap and its energy consumption needs to be reduced [
To cope with all these challenges, designers rely more on mature digital electronics technologies that come with friendly software development tools. Following this development, a Field-Programmable Gate Array (FPGA) has become an extremely cost-effective means of realizing computationally intensive digital signal processing algorithms to improve overall system performance.
The FIR filter implementation in FPGA utilizing the dedicated hardware resources can effectively achieve application-specific integrated circuit (ASIC)-like performance while reducing development time cost and risks [
In this paper FDA tool from Matlab mathematical computational package with digital signal processing toolboxes is used to design filter response and generate coefficients tables. In the proposed approach, FIR tool utilizes distributed arithmetic (DA) as shown in
・ It meets specifications with the least number of coefficients;
・ Uses less amount of resources on FPGA for implementation;
・ The weighted approximation error between the desired and actual frequency response is spread evenly across the pass-band and stop-band of the filter thereby minimizing error;
・ Pass-band and stop-band deviations can be specified separately.
Below is the Equiripple equation:
where:
Fs is the sampling frequency;
F-stop is the stop-band frequency;
F-pass is the pass-band frequency;
A-pass is the pass-band attenuation;
A-stop is the stop-band attenuation.
Options | Low-Pass Filter | High-Pass Filter | Band-Pass Filter |
---|---|---|---|
Design Method | FIR Equiripple | FIR Equiripple | FIR Equiripple |
Frequency Specifications | Units: KHz Units: kHz Fs: 1500 F-stop: 300 F-pass: 270 | Units: kHz Fs: 1500 F-stop: 450 F-pass: 480 | Units: kHz Fs: 1500 F-stop1: 270 F-stop2: 480 F-pass1: 300 F-pass2: 450 |
Magnitude Specification | Units: dB A-stop: 54 dB A-pass: 1 dB | Units: dB A-stop: 54 dB A-pass: 1 dB | Units: dB A-stop1: 54 dB A-stop2: 54 dB A-pass: 1 dB |
FIRs have the advantage of being much more realizable in hardware [
where
The value of the constant k is a minimum value for which the expression
where the operator
In FIR filter design, filter frequency response coefficients and the corresponding window type function must be known before filter hardware realization.
The value of variable n ranges between 0 and N, where N is the filter order. A constant M can be expressed as
The FIR filter coefficients are found using the following expression:
For direct realization of FIR filter, it is based on the direct implementation of this expression:
The FIR filter is graphically represented by a direct form approach [
Type of Filter | Frequency Response |
---|---|
Low-Pass Filter | |
High-Pass Filter | |
Band-Pass Filter |
based on specification. Following the same procedure, high-pass and band-pass filters are equally generated based on their specifications.
After designing the filters based on their specifications from Matlab, the Xilinx software package provided by Spartan-6 FPGA board, System Generator is then used for the appropriate FIR FPGA filter implementation for low-pass, high-pass, band-pass filter as shown in Figures 5-9.
Figures 6(d)-(f) analyzed when the input signal is above the cut-off frequency and no output waveforms for low-pass frequency.
Figures 8(d)-(f) represent the output waveforms from Matlab and FPGA for High-pass when the input signal is below
Figures 10(d)-(f) represent the output waveforms from Matlab and FPGA for band-pass when the input signal is below
Figures 10(g)-(i) represent the output waveforms from Matlab and FPGA for band-pass when the input signal is below
When the three filters were combined in parallel with individual specifications, the same output waveforms for all the filters were observed which actually proved the parallelism nature of FPGA. With input signal using random source as shown in Figures 12(a)-(g) verified the comparison between the low-pass, high-pass and band- pass filters simulations from Matlab and FPGA parallel implementation.
In this paper, a ninety two-order low-pass and band-pass and ninety nine-order high-pass FIR filter have been implemented in Spartan-6 LX75T-3FGG676C FPGA board using Xilinx Integrated Software Environment (ISE). The propose idea gives an efficient approach towards the implementation of FIR filter using Simulink and subsequent synthesis on FPGA that suited different applications unlike most previous approaches on a penalty of reducing computation speed.
In addition, below are some of the factors used in evaluating the advantages of FPGA:
1) Time to market?FPGA technology offers flexibility and rapid prototyping capabilities in the face of increased time-to-market concerns. You can test an idea or concept and verify it in hardware without going through the long fabrication process of custom ASIC design. It is easy to implement incremental changes and iterate on an FPGA design within hours instead of weeks;
2) Cost?The nonrecurring engineering (NRE) expense of custom ASIC design far exceeds that of FPGA-based hardware solutions. With FPGA, it means that you have no fabrication costs or long lead times for assembly. This is because system requirements often change over time, the cost of making incremental changes to FPGA designs is negligible when compared to the large expense of re-designing an ASIC;
3) Long-term maintenance?As earlier discussed, FPGA chips are field-upgradable and do not require the time and expense involved with ASIC redesign. Digital communication protocols, for example, have specifications that can change over time, and ASIC-based interfaces may cause maintenance and forward-compatibility
(a)
Categories | Low-Pass Filter | High-Pass Filter | Band-Pass Filter | Parallel Implementation on FPGA |
---|---|---|---|---|
Minimum Period (ns) | 10.57 | 11.16 | 10.14 | 15.03 |
Peak Memory Usage (MB) | 294 | 300 | 294 | 410 |
Power Consumption (mW) | 119 | 127 | 118 | 273 |
challenges. Due to reconfigurable nature of FPGA chips, it can keep up with future modifications that might be necessary. As a product or system matures, you can make functional enhancements without spending time redesigning hardware or modifying the board layout;
4) Performance?The hardware parallelism nature of FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle. Controlling inputs and outputs (I/O) at the hardware level provides faster response times and specialized functionality to closely match application requirements. This again evaluates and validates the parallelism nature of FPGA;
5) Reliability?Due to the fact that software tools provide the programming environment, FPGA circuitry is truly a “hard” implementation of program execution. Processor-based systems often involve several layers of concept to help schedule tasks and share resources among multiple processes. For any given processor core, only one instruction can execute at a time, and processor-based systems are continually at risk of time-critical tasks preempting one another. Because FPGAs do not use OSs, it minimizes reliability concerns with true parallel execution and deterministic hardware dedicated to every task.
This paper discusses the implementation of low-pass, high-pass and band-pass FIR Digital Filters on a FPGA.
The simulation results show that the output waveforms obtained from the software simulations correspond with those from FPGA implementation respectively using hardware co-simulations. Also, the parallel implementation proves that performance of a low-pass filter is not affected by both high-pass and band-pass filter and vice-versa, and the synthesis report equally shows less resource usage, speed increase, cost effectiveness, more flexibility and low power consumption which validate the parallelism nature of FPGA.