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A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.

A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.

ADCs are widely used in many areas, such as music recording, healthcare, radar systems and communication [

range is from to. By adding two comparators with comparison voltages of and to the lower and upper sides of traditional 1.5- bit/stage ADC, the analog quantify domain is a five-domain rather than a three-domain; therefore, this proposed configuration is referred to as a five-domain 1.5-bit/stage ADC. Like in

However, the traditional 1.5-bit/stage ADC can only correct the comparator offsets within. In this research, a five-domain 1.5-bit/stage ADC is developed to increase the comparator offset correction ability to with an added overflow/underflow judgment. Two Matlab behavioral simulations are used to illustrate the improvement of the comparator offset correction ability for the proposed ADC. The first ADC behavioral simulation includes eight traditional 1.5-bit/stage converters followed by a flash ADC, and the second ADC behavioral simulation includes eight trial 1.5-bit/stage converters also followed by a flash ADC. In these simulations, the absolute values of the comparator offsets are set between 0 and. In order to control and narrow research findings, all 1.5-bit/stage ADCs are onlycomplicated by the comparator offsets. In addition, the flash ADCs setting are ideal. In these simulations, the total number of conversions is. The total miscode numbers, and their related comparator offsets, are show in

The transfer function of the traditional 1.5-bit/stage pipeline ADC is given by the following equation [

The transfer function of the proposed five-domain 1.5- bit/stage pipeline ADC is given by the following equation:

This proposed ADC consists of eight 1.5-bit stages followed by a 2-bit flash ADC. There are 12 total output bits, 10usable bits and the first two bits are utilized as overflow/underflow bits.

range; otherwise when they are “10”, the remaining ten bits are usable digital output bits.

The proposed algorithm of the ADC, shown in Figures 4(a) and 4(b), uses of 1 V and the input voltage of 0.4 V. The traditional algorithm is shown in Figures 4(c) and 4(d) uses the same and input values. To prevent the influences from flash-ADCs, all of the threshold voltages are set to be the ideal. In

, , and for all of the comparators. The first two bits are “10” indicating that the remaining ten bits are usable output codes. In _{ref}/4|.

The circuit level implementation of Equation (2) is given by

In Equation (3), the two capacitors are equal. When the required gain is one, the circuit level realization is the same as the traditional technique, and capacitor connects to the corresponding reference voltage. However, a gain of two for cannot be realized through the traditional technique since one of the capacitors is the feedback capacitor. The maximum gain for is the non-feedback capacitor divided by the feedback capacitor, which is one. To extend the domain, a new method is proposed. In this new method need to be set to twice the. The first and the last equations of (3) are

Figures 5(a) and 5(b) are the circuit configurations based on the traditional technique and the proposed algorithm, respectively. is simplified by in the figures. Although the actual configurations are fully differential, the sing-ended the configurations are shown for simplicity. When is high, the converters work on the sample phase, input is sampled on the two capacitors simultaneously. When is high, they work on the amplification phase, the feedback capacitor connects to the output and the non-feedback capacitor connects to the corresponding reference voltage.

The proposed algorithm slightly modifies the analog. Two comparators are added to extend the quantify domains, and two references are used to provide a gain of two for. Since the actual configuration is fully dif-

ferential, can be realized by connecting the ground to the positive input side of the amplifier and the to the negative input side of the amplifier in both configurations. The realization of is similar to the realization of. In the digital domain, only several dislocation and subtraction blocks need to be added.

In order to demonstrate the effectiveness of the domain extension algorithm, a 10-bit pipeline ADC was simulated in MATLAB. The ADC consisted of eight fivedomain 1.5-bit/stage converters and a 2-bit flash ADC. In the simulation, all absolute values of comparator offsets were set to, input frequency was set to 45-MHz, and sample rate was set to 100-MS/s. The Fast Fourier Transform (FFT) plot of this simulation using the traditional method is shown in

The simulated dynamic performance of the ADCs at an 100-MS/s sample rate and a 45-MHz input frequency is summarized in

The decrease of the transistor geometry causes problematic mismatches in width, length and threshold voltage, which leads to significant comparator offsets. These comparator offsets, in turn, greatly limit the performance of ADCs. However, the traditional digital error correction technique can only correct the absolute value of comparator offsets lower than. Therefore, in order to improve the comparator offset toleration ability, a domain extension algorithm has been presented, which can correct the absolute value of comparator offsets within. This new approach involves minor analog and digital modifications and increases the comparator offset toleration ability by 50% with overflow/underflow judgment. Simulation results have revealed significant improvements of SFDR, THD and SNR performance.