C.-H. LIN ET AL.371

(a) (b)

(c)

Figure 19. Digital output characteristics of the single-stage

VTDC with the dynamic-logic phase detector in the differ-

ent process corners compensated using different values of

the control voltage (a) TT corner Vc = 1.10 V; (b) FF corner,

Vc = 1.06V; (c) SS corner, Vc = 1.13 V.

5. Conclusions

This paper presents a single-stage Vernier Time-to-

Digital Converter with sub-gate delay time resolution.

By utilizing the dynamic-logic phase detector that elimi-

nates the dead-zone problem, the single-stage Vernier

Time-to-Digital Converter in this work has demonstrated

a linear digital output characteristic with a 25 ps time

resolution. The presented simulation results have con-

firmed the very important role of the phase detector qual-

ity for the performance of single-stage Vernier Time-

to-Digital Converters with sub-gate delay resolutions.

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