J.-F. HUANG ET AL.

209

e chip fabrication and technical supports with

. Zhao, “Continuous-Time Sigma-Delta

Modulator Design for Low Power Communication

oermund, “A 3.3-mW ΣΔ Modulator for

th the

number of T18-98D-158.

7. References

[1] J. Yu and B

Ap-

plications,” Proceedings of IEEE ASICON, October 2007,

pp. 715-720.

[2] R. H. M. van Veldhoven, B. J. Minnis, H. A. Hegt and A.

H. M. van R

UMTS in 0.18-um CMOS with 70-dB Dynamic Range in

2-MHz Bandwidth,” IEEE Journal of Solid-State Circuits,

Vol. 37, No. 12, 2002, pp. 1645-1652.

doi:10.1109/JSSC.2002.804329

[3] L. Dorrer, F. Kuttner, P. Greco, P. Tor

“A 3-mW 74-dB SNR 2-MHz

ta and T. Hartig

Continuous-Time D

,

elta-

sigma ADC with a Tracking ADC Quantizer in 0.13-um

CMOS,” IEEE Journal of Solid-State Circuits, Vol. 40,

No. 12, 2005, pp. 2416-2427.

doi:10.1109/JSSC.2005.856282

[4] S. R. Norsworthy, R. Schreier

ta-Sigma Data Converters: Theo

and G. C. Temes, “Del-

ry, Design and Simula-

eless Applications,”

a Pipeline

tion,” IEEE Press, New York, 1996.

[5] B. J. Farahani and M. Ismail, “Adaptive Sigma Delta

ADC for WiMAX Fixed Point Wir

IEEE Midwest Symposium on Circuits and Systems, Vol.

1, Covington, 7-10 August 2005, pp. 692-695.

[6] T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro

and S. W. Harston, “A Cascaded Sigma-Delt

A/D Converter with 1.25 MHz Signal Bandwidth and 89

dB SNR,” IEEE Journal of Solid-State Circuits, Vol. 32,

No. 12, 1997, pp. 1896-1906. doi:10.1109/4.643648

[7] R. Jiang and T. Fiez, “A 14-bit Delta-Sigma ADC with

8X OSR and 4-MHz Conversion Bandwidth in A 0.18 um

CMOS Process,” IEEE Journal of Solid-State Circuits,

Vol. 39, No. 1, 2004, pp. 63-74.

doi:10.1109/JSSC.2003.820877

[8] A. Bosi, A. Panigada, G. Cesura

80 MHz 4x Oversampled Cascaded

and R. Castello, “An

ΔΣ-Pipelined ADC

In-

ators for High-Speed A/D Conver-

ara, “A 70-mW 300

with 75 dB DR and 87 dB SFDR,” IEEE International

Solid-State Circuits Conference, 2005, pp. 174-175.

[9] F. Munoz, K. Philips and A. Torralba, “A 4.7 mW 89.5 dB

DR CT Complex DS ADC with Built-In LPF,” IEEE

ternational Solid-State Circuits Conference, February

2005, pp. 500-501.

[10] J. A. Cherry and W. M. Snelgrove, “Continuous-Time

Delta-Sigma Modul

sion,” Kluwer, Boston, 2000.

[11] S. Paton, A. D. Giandomenico, L. Hernandez, A. Wies-

bauer, T. Potscher and M. Cl-MHz

CMOS Continuous-Time ΣΔ ADC with 15-MHz Band-

width and 11 Bits of Resolution,” IEEE Journal of Sol-

id-State Circuits, Vol. 39, No. 7, July 2004, pp. 1056-

1063. doi:10.1109/JSSC.2004.829925

[12] G. Mitteregger, C. Ebner. S. Mechnig, T. Blon, C. Holu-

igue and E. Romani, “A 20-mW 640-MHz C

tinuous-Time ΣΔ ADC with 20-MHz Signal Band- width,

80-dB Dynamic Range and 12-Bit ENOB,” IEEE Journal

of Solid-State Circuits, Vol. 41, No. 12, 2006, pp.

2641-2649. doi:10.1109/JSSC.2006.884332

[13] S. Karthikeyan, S. Mortezapour, A. Tammineedi and E.

Lee, “Low-Voltage Analog Circuit Design Based on Bi-

ased Inverting Opamp Configuration,” IEEE Transac-

tions on Circuits and Systems II: Analog and Digital

Signal Processing, Vol. 47, No. 3, 2000, pp. 176-184.

doi:10.1109/82.826743

[14] L. Lamarre, M. Louerat and A. Kaiser, “A Simple 3.8 mW

300 MHz, 4-Bit Flash A

,

nalog-to-Digital Converter,” Pro-

ceedings of the SPIE, Vol. 5837, No. 51, 2005, pp. 825-

832. doi:10.1117/12.608343

[15] B. Razavi, “Principles of Data Conversion System De-

sign,” IEEE Press, New York, 1995.

ed Comparator for

[16] J. Chen, S. Kurachi, S. Shen, H. Liu, T. Yoshimasu and Y.

Suh, “A Low-Kickback-Noise Latch

High-Speed Flash Analog-to-Digital Converters,” Inter-

national Symposium on Communications and Information

Technologies, Beijing, 12-14 October 2005, pp. 250-253.

[17] Z. Li and T. S. Fiez, “A 14-Bit Continuous-Time Delta-

sigma A/D Modulator with 2.5 MHz Signal Bandwidth,”

IEEE Journal of Solid-State Circuits, Vol. 42, No. 9,

2007, pp. 1873-1883. doi:10.1109/JSSC.2007.903086

[18] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. San-

sen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS

DAC,” IEEE Journal of Solid-State Circuits, Vol. 33, No.

12, 1998, pp. 1959-1969. doi:10.1109/4.735536

[19] T. H. Kuo, K. D. Chen and H. R. Yeng, “A Wideband

CMOS Sigma-Delta Modulator with Incremental Data

Weighted Averaging,” IEEE Journal of Solid-State Cir-

cuits, Vol. 37, No. 1, 2002, pp. 11-17.

doi:10.1109/4.974541

[20] F. Gerfers, M. Ortmanns and Y. Manoli

Power-Efficient Contin

, “A 1.5-V 12-Bit

uous-Time Third-Order ΣΔ Mod-

ulator,” IEEE Journal of Solid-State Circuits, Vol. 38, No.

8, 2003, pp. 1343-1352. doi:10.1109/JSSC.2003.814432

[21] L. J. Breems, R. Rutten and G. Wetzker, “A Cascaded

Continuous-Time ΣΔ Modulator with 67-dB Dynamic

Range in 10-MHz Bandwidth,” IEEE Journal of Sol-

id-State Circuits, Vol. 39, No. 12, 2004, pp. 2152-2160.

doi:10.1109/JSSC.2004.836245

[22] S. D. Kulchycki, R. Trofin, K. Vleugels and B. A. Woo-

ley, “A 77-dB Dynamic Range, 7.5-MHz Hybrid Con-

tinuous-Time/Discrete-Time Cascaded ΣΔ Modulator,”

IEEE Journal of Solid-State Circuits, Vol. 43, No. 4,

2008, pp. 796-804. doi:10.1109/JSSC.2008.917499

[23] M. Anderson and L. Sundstrom, “Design and Measure-

ment of a CT ΔΣ ADC with Switched-Capacitor Switched-

Resistor Feedback,” IEEE Journal of Solid-State Circuits,

Vol. 44, No. 2, 2009, pp. 473-483.

doi:10.1109/JSSC.2008.2010978

[24] A. Hart and S. P. Voinigescu, “A 1 GHz Bandwidth Low-

Pass ΔΣ ADC with 20-50 GHz

Adjustable Sampling

Rate,” IEEE Journal of Solid- State Circuits, Vol. 44, No.

5, 2009, pp. 1401-1414. doi:10.1109/JSSC.2009.2015852

MOS Con-

Copyright © 2011 SciRes. CS