
M. KUMAR ET AL.
Copyright © 2011 SciRes. CS
194
Table 3. Comparison of
VCO performance.
Vdd (V) Technology (µm) Power consumption VCO designs Operating frequency (GHz)
[1] 2.17 - 2.73 0.9 0.18 2.7 mW
[5] 0.39 - 1.41 1.8 0.18 12.5 mW
[10] 0.12 - 1.3 0.5 0.18 0.085 mW
[13] 16.8 mW
[16] 0.65 - 1.6 1.8 0.18 39 mW
Present work [3 stages XNOR] [
ent work [5 stages XNOR] 1 [465.7
ent work [3 stages XOR] [296.3 µW
nt work [5 stages XOR] 1. [493. µW
1.57 - 3.57 1.8 0.090
1.900 - 0.964 1.8 0.18 279.429 - 16.515] µW
Pres.152 - 0.575 1.8 0.18 15 - 27.526] µW
Pres1.917 - 1.029 1.8 0.18 93 - 19.051]
Prese049 - 0.5651.8 0.18 989 - 31.753]
perform in terms of power consumptiotput
frequenircuits.
4. Con
reported work improved power efficient designs for
CO with XNOR
iation [1.900 - 0.964] GHz with devia-
ption from [279.429 - 16.515] µW.
o. 7, July 2008, pp.
8.921574
ancen and ou
cy range than compared c
clusions
In
three and five stages CMOS ring VCOs have been pre-
sented. In first methodology design with XNOR delay
ages have been presented. Three stages Vst
shows frequency var
on in power consumti
Five stages XNOR delay based VCO gives output fre-
quency range [1.152 - 0.575] GHz with power consump-
tion variation [465.715 - 27.526] µW. In the second me-
thodology VCO designed with three stages XOR based
delay cell shows frequency variation [1.917 - 1.029] GHz
with power consumption variation [296.393 - 19.051] µW.
Finally the VCO designed with five stages XOR delay
cells shows frequency variation [1.049 - 0.565] GHz with
power consumption variation [493.989 - 31.753] µW.
Proposed designs have been compared with previously
reported design and present approach shows significant
power saving with wide tuning range.
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