
Circuits and Systems, 2011, 2, 162-169
doi:10.4236/cs.2011.23024 Published Online July 2011 (http://www.SciRP.org/journal/cs)
Copyright © 2011 SciRes. CS
A Review of PVT Compensation Circuits for Advanced
CMOS Technologies
Andrey Malkov, Dmitry Vasiounin, Oleg Semenov
Freescale Semicond ucto r, Moscow, Russia
E-mail: osemenov@freescale.com
Received January 30, 2010; revised April 18, 2011; accepted April 25, 2011
Abstract
The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers
to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and
output load variations. As the interface speed grows up, the output drivers have been important component
for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the
output drivers. The output driver impedance compliance with the transmission line is a key factor in noise
minimization due to the signal reflections. In this paper, the different implementations of PVT compensation
circuits are analyzed for cmos45 nm and cmos65 nm technology processes. One of the considered PVT com-
pensation circuits uses the analog compensation approach. This circuit was designed in cmos45 nm technol-
ogy. Other two PVT compensation circuits use the digital compensation method. These circuits were de-
signed in cmos65 nm technology. Their electrical characteristics are matched with the requirements for I/O
drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless
design team for mobile phones and later was re-used for other high speed interface designs. In conclusion,
the advantages and disadvantages of considered PVT control circuits are analyzed.
Keywords: PVT Compensation, PVT Control Circuit, Process Variation, DDR Interface, I/O Driver
1. Introduction
In any manufacturing step during the fabrication process
of ICs, there are target specifications and there are man-
ufacturing tolerances around each specification. For ex-
ample, the gate oxide thickness specification translates to
slower devices (higher threshold voltage) for thicker ox-
ides and faster devices for thinner oxides (lower thresh-
old voltage). If such devices were used as a driver ele-
ment, large variations in driver strengths and slew rates
from the pre-driver should be expected. This is turn af-
fects the timing of the outgoing signals.
Providing the higher data processing rate and interface
speed are becoming more important to the evolution of
multimedia environment. For example, the speed of
modern storage interfaces (ATA/ATAPI-6 standard) has
rapidly increased up to 100 MB/s [1]. The recent high-
performance interfaces like DDR2, DDR3, USB and
Serial ATA require their output drivers to provide a
minimum variation of rise and fall times over process,
voltage, and temperature (PVT) and output load varia-
tions. As the interface speed grows up, the output drivers
have been important component for high quality signal
integrity, because the output voltage levels and slew rate
are mainly determined by the output drivers. Any de-
crease in the skews variation depending on the PVT
variations can usually be translated into better timing
budgets and signal integrity, resulting in the increase of
system I/O speed. To achieve good signal integrity, slew
rate also must be kept constant over PVT variations.
Large slew rate induces significant switching noise
(Ldi/dt noise) and small slew rate decrease the signal
timing margin. One method to improve system speed is
to provide circuit compensation. The compensation al-
lows the designer to speed up the slower I/O driver and
receiver speeds and increase the driver strength for the
slow part. At the same time, the fast part is slowed down
to match the slow part in speed and drive strength. Vari-
ous compensation architectures have been previously
reported for PVT variation [2-5] and most of them use
external resistors to generate a bias current. Generally,
the PVT control circuits can be classified on two types
with (1) analog and (2) digital compensation methods, as
it shown in Figure 1. In this paper, the different imple-