M. KUMNGERN

131

RL2) are replaced by MOS resistor as shown in Figure 10

According to (8), when Rin and RL1 are identical to obtain

Vav, then Vrms can be obtained by setting RL2/Rin = 1.111.

In this case, the aspect ratios (W/L) of MOS transistors,

MR1 and MR2, for Rin, RL1 and RL2 are 2 m/2 m, 2 m/

2 m and 1.8 m/ 2m, respectively (Rin = RL1 = 3.457 k

and RL2 = 3.844 k). A sinusoidal input with Vin = 200 mV

and f = 1 MHz was applied to the converter and C = 1 nF.

The supply voltages for DDCC are selected as VDD =

−VSS = 2.5 V and the bias voltage is set as VB = −1.7 V.

The multiple-output DDCC can be obtained by adding

additional current mirrors. Figure 11 shows the simula-

tion results for Vavg = 126.63 mV and Vrms = 140.45 mV,

with ripple less than 2%. In this case, the RMS voltage

converter for both sinusoidal (output Vrms) and symmet-

rical square (output Vavg) waveform can be obtained. To

achieve this case, the buffer circuits should be used.

5. Conclusions

In this paper, a new DDCC-based full-wave rectifier has

been presented. The proposed circuit comprises only two

DDCC which is suitable for IC implementation. The-

proposed circuit has high-input and low-output imped-

MR

2

MR

1

S

e

D

V

eq

eq

Figure 10. MOS resistor.

Figure 11. Simulated Vavg and Vrms for sinusoidal input with

amplitude of 200 VPeak and frequency of 1 MHz.

ance terminals, hence it easy to drive loads without using

a buffering device. It can be applied to various nonlinear

analog signal processing circuits. The performance of the

proposed circuit is confirmed from PSPICE simulation

results. Simulation results show that the proposed recti-

fier have excellent temperature stability. The application

of proposed rectifier to pseudo RMS-to-DC conversion is

also included.

6. References

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