D. Jan
in parallel towards the metal1 layer. The dielectric in this structure is considerably thicker than in the 2 previous
cases.
Although this technique looks very simple and attractive, the practical implementation and the correct com-
ponent dimensioning are not straightforward at all and require a careful optimization process.
Proper IC Technology Choice
The third method to increase the power efficiency deals with a proper choice of IC technology. Of course, the
specified maximum output voltage of the Dickson charge pump will set a lower limit for the high-voltage han-
dling capability of the smart power IC technology, but also the performance of the integrated capacitors and
transistors are very important selection criteria. Indeed, competitive technologies with similar voltage ratings
may offer different capacitor structures with completely different values of the parasitic capacitance, resulting in
significantly different power efficiency levels. Also the specific performance (on-state resistance as well as pa-
rasitic capacitance) of the P-type and N-type high-voltage DMOS transistors in the pulse-driven active diode
circuit of Figure 4 will largely affect the overall power efficiency.
To illustrate the importance of the capacitor structure, we’ll consider the example of the 100 V 0.7 µm I2T
technology (Intelligent Interface Technology) of ON Semiconductor. Figures 6-8 show a vertical cross section
of 3 different kinds of integrated capacitors in this technology. Figure 6 depicts a capacitor between a poly-sil-
icon layer at the top and a highly doped N+ implantation at the bottom, with a very thin dielectric in between.
Figure 7 represents a capacitor structure between 2 poly-silicon layers, with a somewhat thicker dielectric. Fi-
nally, Figure 8 shows a sandwich structure where the shorted poly-silicon and metal2 layers form 2 capacitors
in parallel towards the metal1 layer. The dielectric in this structure is considerably thicker than in the 2 previous
cases.
Based on the information from Table 1, we can easily select the most appropriate capacitor type for every in-
dividual stage in the Dickson charge pump. In the first set of stages, where the capacitor operating voltage is li-
mited to values below 30 V, the PP capacitor is selected as it is superior in terms of percentual parasitic capacit-
ance. However, for the last stages with operating voltages in excess of 30 V, the MM capacitor is the only option
because of the voltage rating. The very bad corresponding percentual parasitic capacitance towards the substrate
is then something we have to live with and it means that for charge pumps with an output voltage much higher
than 30 V, the overall power efficiency of the generator will be very low!
For charge pumps with very high output voltages it is therefore advisable to compare several smart power IC
technologies and to select the one that offers a type of high-voltage capacitor with the lowest possible percentual
parasitic capacitance towards the substrate. Take for instance the 80 V I3T technology (Improved Intelligent In-
terface Technology) of ON Semiconductor, which is much more advanced than the 100 V I2T technology as it is
based on a 0.35 µm CMOS core process instead of the older 0.7 µm process. Due to the fact that this 80 V I3T
technology allows much smaller metal track widths and spacings as well as 5 metal levels instead of only 2, it
becomes possible to integrate multi-metal capacitors with a kind of staggered “finger”-structure design of the 2
electrodes as shown in the schematic cross-sectional view of Figure 9.
This type of capacitor design makes optimal use of the horizontal and vertical dimensions (there is capacit-
ance between neighboring metal stripes in horizontal and vertical direction) to get the maximum capacitance for
a given amount of silicon area while keeping the parasitic capacitance towards the substrate to a minimum. This
is clearly evidenced in Table 2, comparing the performance of the metal1-metal2 -poly capacitor (MM) in the
100 V 0.7 µm I2T technology and the multi-metal “finger” capacitor (MF) in the 80 V 0.35 µm I3T technology.
As could be expected, the high-voltage MF capacitors in the 80 V 0.35 µm I3T technology exhibit a 4 times
lower percentual parasitic capacitance than the high-voltage MM capacitors in the 100 V 0.7 µm I2T technology.
This makes the 80 V 0.35 µm I3T technology the preferred choice for integrating high-voltage Dickson charge
pumps with maximum power efficiency.
Table 1. Comparison of different capacitor types in the 100 V 0.7 µm I2T technology.
Capacitor type Max. voltage (V) Specific capacitance (fF/µm2) Parasitic capacitance (fF/µm2)
PN 12 0.75 0.27 (36%)
PP 30 0.345 0.079 (23%)
MM 100 0.091 0.057 (63%)