Journal of Software Engineering and Applications, 2011, 4, 320-328
doi:10.4236/jsea.2011.45036 Published Online May 2011 (http://www.SciRP.org/journal/jsea)
FPGA Simulation of Linear and Nonlinear
Support Vector Machine
Davood Mahmoodi1, Ali Soleimani1, Hossein Khosravi1, Mehdi Taghizadeh2
1Department of Electrical Engineering and Robotic, Shahrood University of Technology, Shahrood, Iran; 2Department of Electrical
Engineering, Kazerun Branch, Islamic Azad University, Kazerun, Iran
Received April 10th, 2011; revised April 30th, 2011; accepted May 8th, 2011.
ABSTRACT
Simple hardware architecture for implementation of pairwise Support Vector Machine (SVM) classifiers on FPGA is
presented. Training phase of the SVM is performed offline, and the extracted parameters used to implement testing
phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pairwise
classifiers is designed in parallel and simultaneously. In order to realization, a dataset of Persian handwritten digits in
three different classes is used for training and testing of SVM. Graphically simulator, System Generator, has been used
to simulate the desired hardware design. Implementation of linear and nonlinear SVM classifier using simple blocks
and functions, no limitation in the number of samples, generalized to multiple simultaneous pairwise classifiers, no
complexity in hardware design, and simplicity of blocks and functions used in the design are view of the obvious char-
acteristics of this research. According to simulation results, maximum frequency of 202.840 MHz in linear classifica-
tion, and classification accuracy of 98.67% in nonlinear one has been achieved, which shows outstanding performance
of the hardware designed architecture.
Keywords: Hardware Architecture, Support Vector Machine, FPGA, Persian Handwritten Digits, System Generator
1. Introduction
Today, many algorithms in the fields of signal proc-
essing, including speech processing, image processing,
machine vision, data mining and pattern recognition, is
developed on software and every day new progress in
their development is achieved. Many of these algo-
rithms run with lower frame rates because of computa-
tional complexity. Fast and real-time processing re-
quirement yield hardware implementation of these al-
gorithms. But, implementing these algorithms on
hardware such as microprocessors, DSP or FPGA pro-
cessors continue to be an important challenge [1].
Recently FPGAs have been introduced as one of the
hardware used in the field of digital signal processing
and provided acceptable results in real-time applica-
tions, using parallel processing [2].
SVM is one of the trusted and ultra high-perform-
ance algorithms, has been widely used in the fields of
linear and nonlinear classification and regression prob-
lems [3]. As regards that the structure of SVM includes
a second optimization process, so practical applications
of this classifier will be limited, due to the computa-
tional complexity and power consumption of training
phase.
Obviously useful applications of online SVM require
a hardware implementation suitable for training and
testing phase. But considering the type of application,
training phase of SVM can be performed offline in a
computer by software. Therefore in these cases only
testing phase of the SVM, that includes a decision
function for classification target and is performed very
fast, will be implemented on hardware [4].
Anguita [5] proposed a fully digital hardware struc-
ture for implementation of testing and training phase of
SVM using linear and RBF kernel functions. The pro-
posed structure in addition to consuming too much
hardware resources, has not an acceptable processing
speed. Maximum frequency obtained by Anguita was
35.3 MHz. Faisal Khan [6] avoided of fixed-point
computations and used the logarithmic number system
for implementing testing phase of linear SVM. Al-
though the proposed structure is suitable for hardware,

FPGA Simulation of Linear and Nonlinear Support Vector Machine321

b
but always may be difficulties in converting real num-
bers to their equivalent logarithmic. Ramirez [4] im-
plemented a linear SVM for classification of three-
dimensional MRI images. Classification accuracy and
processing time was 95% and 109.7s respectively,
which was 5% less and 1.84 times more than a 550
MHz PC. In this research maximum frequency of
202.840 MHz in linear classification, and classification
accuracy of 98.67% in nonlinear one has been achieved,
while processing time is much more than PC, which is
comparable in literatures [1,7,8].
The rest of this paper is organized as follow: after
introduction, Section 2 describes the basics of linear,
nonlinear and multiclass SVM. In Section 3 proposed
algorithm for SVM hardware implementation, include-
ing software implementation and hardware architecture
design has been described. Finally our simulation re-
sults are given in Section 4, followed by conclusion
and suggestions in Section 5.
2. Support Vector Machine
SVM is a technique of classification and regression
introduced in 1990s by Vapnik [9,10]. SVM is essen-
tially a binary classification, but possible to classify
samples of multiple classes. Also it can be used to
solve either linear and nonlinear classification or re-
gression problems.
2.1. Linear SVM
Consider a linear classification problem aiming to find
optimal separating hyperplane with maximum margin.
Suppose xi is the feature vector set of training samples
that are linearly separable and have been labeled in
classes1 and 2, as Figure 1. There might be some data
that fall into the margin, called slack variables.
So decision function is defined as follow:


T
dsignxwx (1)
Optimal separating hyperplane can be obtained by
solving the following dual Lagrange problem:

1,1
1
1
Maximize 2
0
Subject to
0
NN T
diijij
iij
i
N
ii
i
Lyy
C
y














xx 
ij
(2)
in which C is a trade-off parameter between maximiza-
tion the margin and minimization the error, and is deter-
mined by user [11].
By solving dual Lagrange function, α is obtained. Sub-
sequently w and b are achieved too, according to the
Figure 1. Optimal separating hyperplane with maximum
margin and slack variables.
following:
1
SV
ii i
i
x
y 

 w (3)
T
i
bywx
i
(4)
where SV is the number of support vectors.
Now we can classify an unknown data x, by utilizing
(3) and (4) into the decision function Equation (1), which
yield to the following equation:

1
SV
T
iii
i
ydsign 


b





xx
x
(5)
2.2. Nonlinear SVM
A question that is being asked here is that what to do if
data are not linearly separable? Is it possible to general-
ize the idea of a linear SVM to nonlinear systems? Ex-
tensive studies conducted in this area resulted in Mercer
theory [12]. The idea behind this theory is to transfer
vector x from limited space (input space) to the higher
space (feature space), using Hilbert conversion, as Fig-
ure 2. In this context a vector x in the feature space is
converted into the φ(x).
According to this theorem, decision function of
Nonlinear SVM can be acquired as following:
Figure 2. Transferring a data x form input space (left) into
the feature space (right).

FPGA Simulation of Linear and Nonlinear Support Vector Machine
322


1
,
SV
ii i
i
dyK
s
ign b 






xxx

x
(6)
where:

1
,
SV
iiii
i
by yK 


xx (7)
in which the term has been replaced with
a kernel function defined as follow:
 
T

i
x
 
,T K  
ii
xxx x (8)
where, well-known kernel functions have been intro-
duced in literatures [13-15].
2.3. Multi Class SVM
SVM is a binary classifier, but some methods can be
used to solve multi-class problems with this classifier.
Four methods of multi-class SVM are:
• One against All Method
• Pairwise Classifiers Method
• Error-correcting Output Code (ECOC) Method
• All Classes at Once Method
In one against all method, if we have n class, n binary
SVM classifier will be formed, so that in i-th classifier,
class i is separated from the others. But in this status still
there will be unclassified regions according to Figure 3
[11].
To solve this problem, Krebel [16] proposed pairwise
classifiers method, in which to solve n class problem,

12nn binary classifier will be formed. This method
compared to one against all is better but still there will be
unclassified region according to Figure 4.
In the pairwise classifier method, for classification of
an input data x, in each binary decision function dij(x) a
class is selected, and finally the one with the most votes
is selected as desired class.
3. The Proposed Algorithm for SVM
Hardware Implementation
To implement SVM classifier architecture on the hard-

Class1
Class2
Class3
Figure 3. Unclassified regions in one against all method.
Class1
Class2
Class3
Figure 4. Unclassified region in pairwise classifiers method.
ware, we must first perform learning phase of the SVM,
which has a complicated algorithm, offline on the soft-
ware, and then use extracted parameters to implement
testing phase on the hardware. In this research training
phase of the SVM is implemented in the MATLAB
software environment utilizing libsvm [17] model, and
the graphical hardware simulator, System Generator, will
be used to design and implement of testing phase.
In order to realize designed architecture and desired
results, three different classes of data related to Persian
handwritten digits, 1, 4 and 8, are used for training and
testing samples of the SVM [18]. We named class1 for 1,
class2 for 4, and class3 for 8. So the architecture will be
designed for a 3-class SVM, according to pairwise
method. 800 data from each class (total 2400 samples) is
provided. From each class of data, 600 samples have
been used for training and 200 samples for testing. Data
has feature vector dimension of 7 and 24, which have
been extracted by using of geometric moments approach
[19]. We use 7-d data for linear and 24-d data for nonlin-
ear SVM.
3.1. Software Implementation of SVM
Before hardware implementing of the SVM architecture,
it is necessary to run both training and testing phase in
MATLAB. The target is to get the lowest classification
error rate by changing various parameters. In additions,
in that lowest error rate, necessary parameters will be
extracted for offline classification on the hardware. In
order to implement software SVM, despite SVM toolbox
of the MATLAB, many other codes written by research-
ers have been proposed. Libsvm model has been intro-
duced as one of the best and trusted tools for implemen-
tation of SVM, and is used in most of academic papers
and researches, so we utilize Libsvm too.
In general, before SVM implementation, the type of
kernel function must be specified. We used linear and
Gaussian kernel functions to implement SVM.
3.2. SVM Software Implementation with Linear
Kernel
Linear kernel is the simplest type of kernel functions.

FPGA Simulation of Linear and Nonlinear Support Vector Machine
323
Figure 6. Diagram curve of nonlinear classification error
rate versus changing parameter γ.
Figure 5. Diagram curve of linear SVM classification error
rate versus changing parameter C.
stead, there is a parameter γ in Gaussian kernel, affecting
the classification error rate, which defined as following:
Because of its simplicity in structure, and fast computa-
tion, it is a very good choice to for hardware implemen-
tation. In this research, experiments show that by chang-
ing the parameter C, the classification error rate will be
in change too. In order to achieve the lowest error rate,
we draw diagram curve of error rate versus changing
parameter C of SVM structure. Figure 5 shows this dia-
gram in classification of Persian handwritten digits with
7-d data.
2
12

  (9)
Choosing appropriate gamma value is a very important
issue to find the optimal classification error rate. Exact
formulation doesn’t exist to calculate an appropriate
value of gamma, and often try and error method is used
to get that. In order to attain that value in nonlinear clas-
sification of Persian handwritten digits with 24-d sam-
ples, a diagram curve of error rate versus changing of
gamma is considered in Figure 6, which shows that
gamma = 0.95 offers the lowest error rate. So in the next
step we use gamma = 0.95 and again run training and
testing phases of SVM. Table 2 shows numerical results
of this classification.
Figure 5 shows that the best classification error rate is
obtained at C = 5500. But if the same value of C is used
for implementation on hardware, have to assign much
number of bits. If the value of C is equal to 100, due to
the low number of bits, desired hardware design can be
implemented, while increasing in error rate is not very
sensible. 3.4. Hardware Architecture Design
Table 1 shows numerical results of linear SVM classi-
fication by using C = 100, in which SV and b indicate the
number of support vectors and bias term, respectively.
Figure 7 shows block diagram of hardware architecture
design for 3-class SVM classification according to si-
multaneous pairwise classifiers method. This design is
the same for linear and nonlinear SVM, but only kernel
block is differently designed.
3.3. SVM Software Implementation with
Nonlinear Kernel
Gaussian kernel function is one of the kernel functions
that mostly has been used in support vector machines,
and provided much better results compared to other ones
[20]. In this research, the Gaussian kernel function is
used for training and testing nonlinear SVM. Here the
results show that by changing the parameter C, classifi-
cation error rate will not be changed anymore. But in-
3.5. System Generator Design of Linear SVM
Before FPGA implementation, in order to simplify com-
putational operations it is better to merge dot product of
vectors α and y into a new vector called yα. Figure 8
shows matrix form of linear SVM decision function for
classification of Class1 & 2, i.e. d12(x).
Table 1. Numerical results of linear SVM classification with
C=100.
Table 2. Numerical results of nonlinear SVM classification
with γ = 0.95.
Class1 & 2 Class1 & 3 Class2 & 3
Class1 Class2 Class1 Class2 Class1Class2
SV 35 35 6 7 243 243
b –0.7895 3.7228 –10.4076
Error
Rate 10.25% 10.5% 20.75%
Class1 & 2 Class1 & 3 Class2 & 3
Class1Class2Class1 Class2 Class1Class2
SV 19 22 18 18 33 35
b–3.8358 –3.2601 –3.1587
Error
Rate 1.5% 0.5% 1.5%

FPGA Simulation of Linear and Nonlinear Support Vector Machine 324
Figure 7. Block diagram of 3-class SVM hardware architecture design.
To design hardware architecture of above function, a
combination of series and parallel methods have been
used. Figure 9 shows part of designed architecture using
System Generator. Each array of rows of matrix SV is
located in SV ROM 1 to SV ROM 7 outputs, which called
by counter1. Test data are in blocks X_Test ROM1 to
X_Test ROM 7 addressing by Counter 2 with a period of
70 (as the number of support vectors of Class1 & 2).
Vector of yα located in YAlpha ROM which its counter
is the same as SV ROMs. Blocks of Mult1 to Mult7 and
Addsub1 to Addsub6 perform inner product between test
data and support vectors; this result is multiplied by cor-
responding array of yα vector in Mult9. The remaining
operations is sum of this values, that is done serially by
Accumulator and +b blocks.
3.6. System Generator Design of Nonlinear SVM
For implementation of nonlinear SVM, 24-d data from
Persian handwritten digit database has been used. Deci-
sion function equation of Nonlinear SVM with Gaussian
kernel function is as follows:

2
1
exp( )
SV
ii i
i
dyxx 

b

 

x (10)
Due to the structural limitations in the FPGA, it is bet-
ter to simplify above function, before implementation of
it. Suppose that A is a vector as follows:
12
=aa





A (11)
Norm A is defined as:
1,1 1,21,71
2,1 2,22,72
1,11,2 1,31,7
70,1 70,270,770
...
...
... ...... ... ......
...
T
sv svsvy
sv svsvy
xxx x
sv svsvy























Figure 8. Matrix form of linear SVM decision function.

FPGA Simulation of Linear and Nonlinear Support Vector Machine325
b12
-0 . 7890 625
YAlph a ROM
addr
en
z
-1
X_Test ROM 7
addr z
-1
X_Test ROM 6
addr z
-1
X_Test ROM 5
addr z
-1
X_Test ROM 4
addr z
-1
X_Test ROM 3
addr z
-1
X_Test ROM 2
addr z
-1
X_Test ROM 1
addr z
-1
SV ROM7
addr
en
z
-1
SV ROM6
addr
en
z
-1
SV ROM5
addr
en
z
-1
SV ROM4
addr
en
z
-1
SV ROM3
addr
en
z
-1
SV ROM2
addr
en
z
-1
SV ROM1
addr
en
z
-1
Relat i onal
a
b
a=b
z
-1
Register
d
en
q
z
-1
Mult 9
a
b(ab)
z
-3
Mult7
a
b(ab)
z
-6
Mult6
a
b(ab)
z
-3
Mult5
a
b(ab)
z
-3
Mult4
a
b(ab)
z
-3
Mult3
a
b(ab)
z
-3
Mult2
a
b(ab)
z
-3
Mult1
a
b(ab)
z
-3
Delay 4
z
-69
Delay 3
z
-1
Delay 2
z
-13
Delay 1
z
-13
Counter 2
out
Counter 1
en out
Constant 4
69
Constant 3
1
AddSub 6
a b
a + b
z
-3
AddSub 5
a b
a + b
z
-3
AddSub 4
a b
a + b
z
-3
AddSub 3
a b
a + b
z
-3
AddSub 2
a b
a + b
z
-3
AddSub 1
a b
a + b
z
-3
Accumulator
b
rs t
q
+b
a
b
en
a + b
z
-1
Figure 9. Hardware architecture for computation of αiyixTxi.

12
22
12
...aaA (12)
And Square of norm A:

222
12
...aaA

(13)
The above equation can be simpler as follows:

222
12
...aaA

(14)
So we can easily implement 2
i
xx by using (14).
For implementation of exp function, there is a CORDIC
block in System Generator that produces sinh and cosh
outputs. By knowing following equation, exp function
can be implemented utilizing a CORD IC block and an
Adder.


exp xSinh xCosh x

(15)
Figure 10 shows FPGA architecture for computation
of αiyiK(xi, x) in nonlinear Gaussian SVM, while other
parts of design are the same as linear one, except that
here data dimension is 24-d. The value of  is located in
constant2 block.
4. Simulation Results
First step for simulation of designed architecture is to
choose FPGA part number. We use Xilinx Virtex4-
xc4vsx35 device for linear and nonlinear SVM simula-

FPGA Simulation of Linear and Nonlinear Support Vector Machine 326
Figure 10. Hardware architecture for computation of αiyi K(x, xi).

FPGA Simulation of Linear and Nonlinear Support Vector Machine 327
Table 3. Hardware simulation results of linear SVM com-
pared with MATLAB.
tion. Fixed point numbers is used for quantization. For
linear simulation Q24.16 and for nonlinear one Q24.14
quantization format is used. To avoid increasing the word
length in serial computations, truncation method is used.
4.1. Linear SVM Simulation
Table 3 shows FPGA simulation results of linear SVM
hardware architecture compared with software imple-
mentation in MATLAB. Rows of 1 through 3 show the
number of samples of each class that classify into the
correct class or misclassify into the others.
It might seem slightly strange that error rate in System
Generator simulation is lower than MATLAB, but we
know that because of quantization errors in System Gen-
erator maybe some test samples classify into correct class,
while misclassified in MATLAB.
The considerable result of this table is maximum fre-
quency and total time of computation of classification
which are 202.840 MHz and 1.4 ms, respectively.
In Table 4 hardware resources used in Virtex4 device
for implementation of above classifier is shown.
Table 4. Hardware resources used in Virtex4 device for
implementation of linear SVM.
Table 5. Hardware simulation results of nonlinear SVM
compared with MATLAB.
System Generator MATLAB
Class1 Class2Class3 Class1 Class2Class3
Class1 1991 0 199 1 0
Class2 3 194 3 3 195 2
Class3 0 1 199 0 1 199
Error Rate 1.33% 1.17%
Number
of Misclassifie
d
Compared
with MATLAB
1 −
Maximum
Frequency 151.286 MHz, Virtex-IV 2.1 GHz, Intel Cor2Dou
Time of
Computation 0.27 ms 0.11 s
4.2. Nonlinear SVM Simulation
Simulation result of hardware designed architecture of
nonlinear SVM is shown in Table 5. In this case classi-
fication error rate of 1.33% and total time of computation
of 0.27 ms are considerable.
In Table 6 hardware resources used in Virtex4 device
for implementation of nonlinear SVM classifier is
shown.
5. Conclusions
In this research FPGA architecture of linear and nonlin-
ear pairwise SVM classifiers for detection of 3-class of
Persian handwritten digits has been proposed. This de-
sign can be generalized to other SVM classification ap-
plications with no limitation in the number of training
and testing data. Also it is Possible to increase the num-
ber of pairwise classifiers. But there is a restriction only
on the FPGA hardware resources. This problem can be
solved by utilizing multi FPGAs or some external mem-
ory devices.
In order to continue the research, proposing a method
for implementation of other nonlinear kernel functions is
recommended. Since that for a certain application one of
Table 6. Hardware resources used in Virtex4 device for
implementation of nonlinear SVM.
Logic Utilization Available Used Utilization Rate
Slice Flip Flop 30720 11589 37%
4 input LUT 30720 9141 29%
Occupied Slice 15360 7261 47%
Bonded IOB 448 241 53%
BUFG 32 1 3%
RAMB16 192 99 51%
DSP48 192 81 42%
System Generator
MATLAB
Class1 Class2 Class3 Class1 Class2Class3
Class1 200 0 0 200 0 0
Class2 6 169 25 6 15935
Class3 0 41 159 0 42 158
Error Rate 12% 13.83%
Number of
misclassified
compared
with
MATLAB
11 −
Maximum
Frequency 202.840 MHz, Virtex-IV 2.1 GHz, Intel Cor2Dou
Time of
computation 1.4 ms 0.45 s
Logic Utilization Available Used Utilization Rate
Slice Flip Flop 30 720 1422 4%
4 input LUT 30 720 748 2%
Occupied Slice 15 360 849 5%
Bonded IOB 448 167 37%
BUFG 32 1 3%
RAMB16 192 31 16%
DSP48 192 27 14%

FPGA Simulation of Linear and Nonlinear Support Vector Machine
328
the kernel functions respond better classification results
than the others, if the solutions to implement all these
functions exist, the designer will have a tendency to
achieve the best classification accuracy.
Another suggestion is to implement the entire process
of SVM, including training and testing phase, on the
FPGA. Training phase of the SVM includes optimization
problem Equation (2), which has a very time consuming
and complicated process of solution for hardware im-
plementation purpose. If an appropriate and hardware
friendly solution is found to simplify the problem, then
whole process of SVM implemented on the FPGA, so
that no need to implement the training phase in software
environment which may cause quantization errors in
testing phase hardware implementation.
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