Energy and Power En gi neering, 2011, 3, 198-205
doi:10.4236/epe.2011.32026 Published Online May 2011 (http://www.SciRP.org/journal/epe)
A New Structure of Multilevel Inverter with Reduced
Number of Switches for Electric Vehicle Applications
Mohsen Ebadpour, Mohammad Bagher Bannae Sharifian, Seyed Hossein Hosseini
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
Received April 18, 2011; revised April 26, 2011; accepted Ma y 3, 2011
Abstract
Both Hybrid Electric Vehicles (HEVs) and Electric Vehicles (EVs) need a traction motor and a power in-
verter to drive the traction motor. The requirements for the power inverter include high peak power, opti-
mum consumption of energy, low output harmonics and inexpensive circuit. In this paper, a new structure of
multilevel inverter with reduced number of switches is proposed for electric vehicle applications. It consists
of an H-bridge and an inverter in each phase which produces multilevel voltage by switching the dc voltage
sources in series. As the number of switches are reduced, both conduction and switching losses will be de-
creased, which leads to increase the efficiency of converter. The size and power consumption of driving cir-
cuits are also reduced. The proposed three phase inverter can produces more number of voltage levels in the
same number of the voltage source and reduced number of switches compared to the conventional inverters.
This structure minimizes the total harmonic distortion (THD) of the output voltage waveforms. The structure
of proposed multilevel inverter, modulation method, switching losses, THD calculation and simulation re-
sults with PSCAD/EMTDC software are shown in this paper.
Keywords: Cascaded H-Bridge, Electric Vehicles (EVs), Hybrid Modulation, Inverters, Traction Motors
1. Introduction
During the past few years, power electronic engineers
have paid great attention to multilevel inverters as a new
kind of power converter. Multilevel inverters can be di-
vided into three remarkable topologies: diode- clamped
[1-3], flying capacitors [4], and cascade H-bridge cells
with separate dc sources [5-8]. The basic motivation for
the use of these multilevel inverters is the reduction of
voltage stress on the switching devices.
Multilevel inverters are used to drive many electrical
machines such as EVs and HEVs [9-11]. The main ad-
vantages of using multilevel converters for the main trac-
tion drive in EVs include:
1) They are suitable for large VA-rated motor drives,
and traditional 230 V or 460 V motors can be used.
2) Higher efficiency is expected for these multilevel
converter systems because higher voltages can be util-
ized and the switching frequency of the devices is at a
minimum.
3) Low voltage switching devices can be used.
4) No electromagnetic interference (EMI) problem or
common-mode voltage/current problem exists.
5) No charge unbalance problem results from either
charge mode or drive mode.
Development of the electric drive trains for these large
vehicles will result in increased fuel efficiency, lower
emissions, and likely better vehicle performance (accel-
eration and braking). One of the important issues in the
mentioned machines is optimum consumption of energy.
For this reason, power consumption of driving circuits of
machines driving inverter should be reduced. On the
other hand, when inverter switches sustain high voltage,
their switching frequency is restricted. In this state, the
output waveform of inverter is distorted and the reliabil-
ity of the motor is reduced. Therefore, in order to over-
come to the problem, voltage of switches must be de-
creased.
There are several methods to reduce the devise voltage.
One of them is dc-dc converters, which divides the volt-
age by the capacitors connected in series [12]. For in-
stance, in this method, when three capacitors are con-
nected in series, the voltage of each capacitor becomes
one third. The other method to reduce the devise voltage
is cascade H-bridge (CHB) inverter, which increase the
number of output voltage levels by increasing the num-

M. EBADPOUR ET AL.
199
)
)
ber of H-bridges. In this method, when the number of
output voltage levels is increased, the number of
switches is also increased. Therefore, in two mentioned
methods, increase of the number of output voltage levels
makes both multilevel inverter and converter more com-
plicated. Another method to reduce the voltage stress on
the switching device that proposed recently is a multi-
level inverter that uses dc voltage sources by switching
them in series and in parallel [13].
In this paper, a new structure of multilevel inverter
with reduced number of switches for electric vehicle
applications is proposed. The proposed structure has
been reduced the size and power consumption in the
driving circuits. The same number of voltage sources is
needed to output the same number of voltage levels
compared to the conventional CHB inverters. Since,
output voltage waveforms of inverter which are produced
by switching the dc voltage sources in series by this
conversion, the voltage of switches are decreased.
Therefore, switching frequency is not restricted. Then,
this inverter is best choice to use in high speed switching
devices such as traction motor drives. The harmonics of
the output voltage waveforms are also reduced. Capaci-
tors, batteries, and other dc voltage sources can be used
as the voltage sources of the proposed multilevel in-
verter.
2. Structure of the Proposed Multilevel
Inverter
Figure 1 shows a single-phase structure of the proposed
three phase multilevel inverter. As shown in Figure 1,
each phase of inverter is constructed of two parts. Part
one is an H-bridge with dc voltage source equal, 0 and
part two is inverter with dc voltage sources equal
. DC voltage sources V are
independent each other, and 0k
is assumed. The voltage sources of part two can make
using the manner of the switched capacitor. As a result,
the (k – 1) number of voltage sources can be as capaci-
tors. This means simple circuits are required in front of
the multilevel inverter for the voltage sources. Switches
11aan
and 11bbm are the switches that
switching the dc voltage sources in series in each phase.
The proposed inverter is driven by the hybrid modulation
(HM) method [3,14].
V
n
V
2, 
(1,2,,
k
Vk n
SS


0
1,:1:VV2

,kn
SS


Figure 2 shows the series conversion of the dc voltage
sources of the proposed 15-level inverter in
phase a. When the switch 1b becomes ON, the current
flows in the switch 1b, which connect the voltage
source 1 to input of lower H-bridge (Figure 2(a)). As
a result, the voltage AB between the point A and the
point B in Figure 2(a) becomes . On the other
hand, when the switches 1a and 2b S become ON and
the other switches become OFF, the current flows in
switches 1a and 2b, which connect the voltage
sources 1 and 2 V in series and 2AB VV (Fig-
ure 2(b)). Finally, when the switches 1a and 2a
become ON and other switches become OFF, the current
flow in switches and 2a S, which connect the volt-
age sources 13 V in series and 123AB VV
(Figure 2(c)). Using this series conversion of dc voltage
sources, the lower H-bridge outputs in
(3n
1AB
VV
S
S
V
V
S
S
VS
1a
V
1
V
S

2bus
v
S
VV 
21n
S


levels, while the upper H-bridge outputs 10bus vV

. The
each phase of the proposed multilevel inverter outputs
43n

levels by 12bus bus vv

or .
21bus bus
If the conventional CHB inverter is driven by hybrid
modulation method, then 12 switching devices are need
for 11 levels, and 16 switching devices are needed for 15
levels [5]. But, the proposed inverter requires 10 devices
for 11 levels and 12 devices for 15 levels. In addition,
when the ratio of the voltage of the sources 0k
vv
VV

:1:3

is assumed, the proposed inverter requires 10 devices for
15 levels and 12 devices for 21 levels. Therefore, the
proposed inverter can increase the number of output
voltage levels by changing the ratio of the voltage of the
sources like conventional CHB inverter. Consequently,
the more output levels make the larger difference be-
tween the required number of switching devices for pro-
posed multilevel inverter and the conventional CHB in-
verter.
Then, the proposed inverter can be smaller than the
conventional inverters. It leads to the simplicity in struc-
ture of inverter and also improved the reliability of sys-
tem.
Figure 1. Single-phase structure of the proposed 4n + 3
levels inverter.

200 M. EBADPOUR ET AL.
(a)
(b)
(c)
Figure 2. Current flow of the proposed 15-level inverter by
series conversion, (a) V1 connected via the switch Sb1; (b) V1
and V2 are connected in series; (c) V1, V2 and V3 are con-
nected in series.
For high power performance, the dc voltage sources can
be switched in series and in parallel. For example, in this
case, 14 switching devices are needed for 15 levels. In
other conventional inverters such as Switched-Capacitor
(SC) inverters a similar scheme that used in proposed
inverter is also used [14]. However, the SC inverters re-
quire 28 switching devices for 11 levels and 36 switches
for 15 levels. Therefore, the proposed multilevel inverter
requires the less number of switching devices than
Switched-capacitor inverters.
When the proposed inverter is applied to some appli-
cation without reverse power flow, switches 11bbm
SS


in each phase can be replaced by diodes. More number of
the switching devices can be reduced in this case. For
example, when a three phase resistive load is connected
to the output of the proposed inverter, the output current
phases are accorded with the voltage phases and direc-
tions of the currents don’t become reverse to the power
sources.
3. Modulation Method
In this section, the modulation method of the proposed
inverter is explained on the 11-level inverter. Figure 3
shows the modulation method of the proposed 11-level
inverter. As shown in Figure 3, the upper H-bridge of
proposed inverter is driven by pulse width modulation
(PWM) method, while the lower H-bridge is driven by
discontinuous reference waveform. Figure 4 shows the
bus voltage waveform when the proposed 11-level in-
verter is driven by the modulation method as shown in
Figure 3.
Figure 3. Modulation method of the proposed inverter.

M. EBADPOUR ET AL.
201
Figure 4. Voltage waveforms of the phase a bridge.
The reference waveform is made by cutting on the
amplitude of the carrier waveform as shown in Figure 5.
The carrier waveform used here, is a triangle waveform.
The modulation index M is defined as,
05 ees
M
AA (1)
where 0e
A
and es
A
are the amplitude of the reference
and the carrier waveforms, respectively. Switches 5
and are driven by comparing the reference wave-
form 01 with the carrier waveform
S
6
e
S
s
e. As a result, the
voltage ac between the point A and the point C in Fig-
ure 1 appears as shown in Figure 3. Switches 7 and
are driven by comparing the reference waveform
02 with the carrier waveform
vS
8
S
e
s
e. As a result, the volt-
age bc between the point B and the point C in Figure
1 appears as shown in Figure 3. Therefore, as shown in
Figure 3, the output voltage waveform of the upper
H-bridge can be obtained as:
v
1bus
v
1busac bc
vvv (2)
Switches 1a, 1b and 14
are switched ON/
OFF when the reference waveform 01 becomes dis-
continuous as shown in Figure 3. When 1a is OFF,
1b is ON, and 1, are ON, the output voltage of
the lower H-bridge becomes:
S S
Sv
SS
eS
S4 S
2bus
21
2
bus
vVV0
0
(3)
When 1a is ON, is OFF, and , are ON,
becomes:
S1b S1 S4 S
2bus
v
212
4
bus
vVVV (4)
When 1a is OFF, is ON, and , are ON,
becomes:
S1b S2 S3 S
2bus
v
Figure 5. Reference waveform.
21
2
bus
vV0 V

 (5)
When 1a is ON, is OFF, and , are ON,
becomes:
S1b S2 S3 S
2bus
v


212
4
bus
vVV 0 V (6)
Therefore, the output voltage waveform of the lower
H-bridge 2bus appears as shown in Figure 4. The pro-
posed inverter outputs the 11-level voltage waveform by
adding and .
v
1bus
v2bus v
4. Calculation of the Conduction and
Switching Losses
The switching loss of each switching device is calculated
from:
2
s
ds s s
PCfV (7)
where ds , C
s
f
, and
s
V mean the capacitance of the
switch, the frequency of the switch and the voltage of
each switching devices, respectively. Therefore, for cal-
culation of switching losses, both voltage and frequency
of switches must be calculated.
The voltages of each device are different in proposed
inverter. The voltages of the switches 11aan SS


Sa San
VV
in
each phase during their OFF state are 11

,
which satisfy:
12 1
0
2
21
n
Sa SaSank
k
VV VV
n

 

 (8)
The voltage of these switches becomes smaller and
smaller compared to the output voltage when the number
of the levels is increased. The switching frequency of
these switches is twice of the frequency of the reference
waveform. The voltages of the switches 11bbm SS


Sb Sbm
VV
in
each phase during their OFF state are 11

,

M. EBADPOUR ET AL.
202
n
4
4
k
V
8
which satisfy:
1
1
,1,2,,
n
Sbm k
km
VVm


 (9)
The voltages of the switches 1 during their
OFF state are , which satisfy:
SS
1SS
VV
14
1
n
SS
k
VV



 (10)
The voltage of these switches becomes almost equal to
the output voltage. On the other hand, the switching fre-
quency of these switches becomes the same frequency of
the reference waveform. Therefore, an IGBT is suitable
for these switches. The voltages of the switches 58
during their OFF state are , which satisfy:
SS
5SS
VV
58
1
1
21
n
SS k
VV
n
  k V
1
k 
(11)
The voltage of these switches becomes smaller and
smaller compared to the output voltage when the number
of the levels is increased. On the other hand, the switch-
ing frequency of these switches is the carrier frequency.
Then, a MOSFET is suitable for these switches. Conse-
quently, the voltage of the switches driven at high fre-
quency is low.
The switching losses are calculated from following
expressions. According to (7), the switching loss of
the switches and is:
1S
P
1aan
SS

11bbm SS



2
2
10
1
16 1
n
sdsrefdsref
m
PmCfVCfV


 

 (12)
where ref
f
mean the frequency of the reference wave-
form. The switching loss of the switches
is:
2S
P14 SS
2
2
1
4
n
sdsrefk
k
PCf V






8
0
(13)
The switching loss of the switches is:
3S
P
5
SS
2
3
4
sds
PCfV (14)
where
f
means the frequency of the carrier waveform.
Furthermore, when are connected in series, the
conduction loss is calculated from the following
expression:
1n
VV
ercs
P


2
21
cser onion
PRInR
2
I (15)
In (15), on, ion , and R R
I
mean the internal resis-
tance of MOSFET, the internal resistance of IGBT, and
the current flowing in the switches. The first and the
second terms express the conduction loss of the upper
H-bridge, and the conduction loss of the lower H-bridge
of proposed inverter, respectively.
The total conduction loss is calculated from the
following expression:
c
P

22
1
32
n
cionon ion
k
PnkRIRIR


 

2
I (16)
In comparison of conventional multilevel inverters,
both switching and conduction losses are decreased that
this is important in EV applications. Especially, the men-
tioned losses are smaller than the losses of multilevel
inverter that has a similar structure and use the dc volt-
age sources by switching them in series and in parallel.
5. Calculation of Total Harmonic Distortion
For calculation of the total harmonic distortion (THD) in
the proposed multilevel inverter, the amplitude of the
harmonics in the output voltage waveforms of the in-
verter must be calculated. For this case, sing Fourier
analysis to calculate the amplitude of these harmonics.
Based on Figure 6, the amplitude of the nth-harmonic in
the 11-level output can be obtained as:
11n
b
41
11
0
1
2cos sin
π5
cos πsin 5
nk
k
bn
nM
k
nn M


























(17)
The amplitude of the nth-harmonic in the 15-level out-
put also can be obtained as:
15n
b
61
15
0
1
2cos sin
π7
cos πsin 7
nk
k
bn
nM
k
nn M









 















(18)
Figure 6. The output voltage waveform.

M. EBADPOUR ET AL.
203
Table 1 shows the calculated (THD) in 11-level,
15-level and 23-level from expression (17) and (18) with
the switching frequency equal 40 kHz. From Table 1, it
is obvious that the more number of the voltage levels
becomes the less quantity of THD.
6. Simulation Results
In this section, the simulation results of the 11-level and
15-level proposed multilevel inverter carried out using
PSCAD/EMTDC is presented to verify the capabilities of
the proposed topology in generating the desired output
voltage. The condition of 05VV

, 1= 10 V, M =
0.9, the internal resistance of MOSFET
n
VV
R0.54
on

,
and switching frequency f = 40 kHz are applied to pro-
posed inverter.
Figure 7 shows the bus voltage waveforms of the pro-
posed three phase 15-level inverter when the inverter fed
an induction motor with two-pole 460-V 50-Hz 3-hp that
used as traction motor in EVs. In addition, inverter one is
loaded with and the other one is loaded with
an inductive load composed of and
in series. Figure 8 shows the bus voltage
waveforms of the proposed 11-level and 15-level inverter
for phase a. Figure 9 shows the output voltage wave-
forms of the proposed 11-level and 15-level inverter
when the filter inductance L and the filter capacitance C
are and . From Figure 9, the
sinusoidal output voltage waveform is confirmed.
50R
μH
2.5 mH
R
L
50R
560L0.5 μFC
If the ideal switches are used, the amplitude of the pro-
posed 11-level inverters output voltage waveform 11
A
becomes:
 

110 1 222.5
A
MVV VV (19)
The amplitude of the proposed 15-level inverters out-
put voltage waveform 15
A
becomes:
 

1501 2331.5
A
MVV VVV (20)
From expressions (19), (20), and Figure 9, it is con-
firmed that the amplitude of calculated output voltage
waveform in the simulation accorded with the theoretical
amplitude.
Figure 10 shows the output voltage waveforms of the
proposed 11-level and 15-level inverters when the in-
verter loaded with an inductive load composed of
Table 1. Comparision of the calculation THD.
The number of output voltage levels THD [%]
11-level 4.57
15-level 3.50
23-level 2.70
Figure 7. Three phase voltage waveforms of 15-level in-
verter fed induction motor.
(a)
(b)
Figure 8. Calculated bus voltage waveform vbus loaded with
R, (a) 11-level; (b) 15-level.

204 M. EBADPOUR ET AL.
(a)
(b)
Figure 9. Calculated output voltage waveform v0ut loaded
with R, (a) 11-level; (b) 15-level.
(a)
(b)
Figure 10. Calculated output voltage waveform v0ut loaded
with an inductive load, (a) 11-level; (b) 15-level.
2.5 mH
R
L

and 50R

 in series. From Figure 10,
the sinusoidal output voltage waveform is also confirmed.
FFT analysis for both 11-level and 15-level bus voltage
waveforms are shown in Figure 11 . As shown in Figure
11, the amplitude of lower harmonics is very small.
7. Conclusions
A new structure of multilevel inverter with reduced
number of switches for EV applications is proposed. The
proposed inverter can produces more number of voltage
levels in the same number of the voltage source and re-
duced number of switches compared to the conventional
inverters. Therefore, the size and power consumption of
driving circuits of inverter is reduced. The modulation
method and the analysis of the harmonics in output volt-
age waveforms of inverter are shown. Both conduction
and switching losses of proposed inverter are calculated.
The proposed inverter can also reduce the THD of output
voltage waveforms. In addition, since the inverter losses
and voltage stress on the switching devices are low, the
efficiency of proposed inverter becomes higher and
switching frequency is not restricted. Therefore, this
(a)
(b)
Figure 11. FFT analysis for bus voltage waveforms vbus, (a)
11-level; (b) 15-level.

M. EBADPOUR ET AL.
205
inverter is best choice to use in high speed switching
devices such as traction motor drives.
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