**Circuits and Systems**

Vol.06 No.05(2015), Article ID:56536,8 pages

10.4236/cs.2015.65015

Accurate Extraction of Effective Gate Resistance in RF MOSFET

Ikkyun Jo, Toshimasa Matsuoka

Graduate School of Engineering, Osaka University, Osaka, Japan

Email: jo@si.eei.eng.osaka-u.ac.jp, matsuoka@eei.eng.osaka-u.ac.jp

Copyright © 2015 by authors and Scientific Research Publishing Inc.

This work is licensed under the Creative Commons Attribution International License (CC BY).

Received 18 April 2015; accepted 19 May 2015; published 22 May 2015

ABSTRACT

This paper describes the gate electrode resistance of MOSFET and non-quasi-static (NQS) effect for RF operation. The vertical current paths between the silicide layer and poly-silicon are considered in the gate electrode. The vertical current paths are not effective in long-channel devices, but become more significant in short-channel devices. The gate resistance including vertical current paths can reproduce the practical RF characteristics well. By careful separation of the above gate electrode resistance and the NQS effect, the small-signal gate-source admittance can be analyzed with 130-nm CMOS process. Elmore constant (κ) of the NQS gate-source resistance is about five for long-channel devices, while it decreases down to about three for short-channel devices.

**Keywords:**

MOSFET, NQS Effect, Gate Electrode Resistance, Elmore Constant

1. Introduction

CMOS device technology realizing low-power, large-scale integration and low-cost to manufacture is recently matching demands for miniaturization, low-power operation in wireless communication systems [1] -[4] . Scaling CMOS devices also are overwhelming the performance, such as unity-current-gain cut-off frequency f_{t}, against bipolar junction transistors and compound semiconductor devices, which are popular in RF circuits [5] . So, RF system on chip (SoC) integrating from digital domain to RF analog domain can be realized. Although complexity of such a RF SoC increases, its short development time is always forced. In such a situation, precise simulations of analog/RF circuits are important, and more accurate MOSFET model and analysis of parasitic elements are needed for their implementations [6] -[8] .

One of the important issues of the MOSFET model in RF operation is related to effective gate resistance which influences input impedance, maximum oscillation frequency f_{max}, and noise performance [9] -[11] . It is especially important in the design of multi-band and wide-band CMOS low-noise-amplifiers (LNAs) [12] -[15] . The RF input resistance in common-source MOSFET has two factors [8] [16] -[18] . The first is related to the physical gate electrode. The second originates from the channel itself in the intrinsic MOSFET region and its coupling with the gate-source capacitance C_{gs}, which causes a relaxation-time dependent phenomenon of channel charge response for a time-varying input signal, so called non-quasi-static (NQS) effect [19] [20] . The NQS gate-source resistance R_{gsi} of the MOSFET operating in saturation region is approximately given by

(1)

where g_{m} is the transconductance, and the Elmore constant κ is five for long-channel and is reported to be as small as one for short-channel devices [17] . Because the above two resistance factors have a different gate size dependence [18] , their separate analysis is important in scalable MOSFET model and is also useful in RF circuit design [8] . Therefore, the accurate resistance model of extrinsic gate electrode is required in advanced short- channel devices as well as the accurate prediction of κ. The accurate value of κ can be useful in some analytical design approaches of LNA [15] [21] .

In this paper, we present high-accuracy gate electrode resistance model. The model presented includes the vertical current paths between the silicide and poly-silicon layers in MOSFET. By careful separation of the gate electrode resistance and the NQS effect, the small signal gate-source admittance can be analyzed. From these values, the κ is derived.

This paper is organized as follows. Section 2 describes gate electrode resistances with vertical current paths. Section 3 presents a MOS equivalent circuit which includes extrinsic and intrinsic parameters, and mentions method of parameter extraction. In Section 4, some parameters extracted in 130-nm CMOS process as well as κ are verified and discussed. Finally, conclusions are drawn in Section 5.

2. Gate Electrode Resistance of MOSFET

The gate of conventional MOSFET model is composed of gate insulator, poly-silicon, silicide and metal. Figure 1(a) illustrates top-view and cross section of n-channel MOSFET with a gate length L and gate width W in the silicided poly-silicon gate technology. When feeding the signal to gate, it propagates in horizontal direction of the silicide on the gate electrode surface, and then in vertical direction of poly-silicon and gate insulator to effect channel. Gate electrode resistance of the MOSFET is composed of gate contact resistance between connecting the metal and silicide, resistance of the silicide itself, the interface resistance between the silicide and poly-silicon,

(a) (b)

Figure 1. (a) Top-view and cross section of MOSFET (both-side gate connection) and (b) equivalent circuit of gate unit element.

and vertical resistance of the poly-silicon itself [22] . The interface resistance is important in the vertical signal propagation [11] , and its typical values are about 25 Ωμm^{2} (TiSi_{2}) [11] and about 2 ~ 3 Ωμm^{2} (NiSi) [23] . In long-channel MOSFET, vertical current paths of the gate electrode are less effective than gate contact and silicide resistance. However, as gate length decreases, the influence of vertical current paths becomes more effective. As gate width decreases, the horizontal resistance decreases, while the vertical resistance increases inversely proportional to the gate width.

Each parts of gate electrode resistance can be expressed with lumped elements for the signal path length in a horizontal gate width direction dz using a transmission line model as illustrated in Figure 1(b), which is similar to that in silicided diffusion region [24] . Here, R_{cg} is unit gate contact resistance between the silicide and poly- silicon, ρ_{sili} is the sheet resistivity of the silicide, ρ_{int} is an interface resistivity between the silicide layer and poly-silicon, ρ_{vp} is the vertical resistivity of poly-silicon layer per unit dimension. C_{ox} is unit capacitance of the gate insulator. For simplification in mathematical expression, , ,. When C_{gc} is defined as the capacitance between the gate and channel, we can consider it as.

Considering the steady state at the angular frequency ω in Figure 1(b), the total admittance of vertical current path elements for unit signal propagation length on the gate electrode surface, Y_{vp}, is given by

(2)

From the manipulation described in Appendix, the gate electrode resistance seen from the gate contact position for unit gate finger with length W_{f} is expressed as

(3)

where k is 1 and 1/4 for a single-side and a both-side gate connections, respectively.

Additionally, considering the gate contact between the silicide and metal as well as the gate extension to the channel area in a similar way based on the previous work [7] , the gate electrode resistance for the number of gate finger N_{f} is expressed as

(4)

where W_{ext} is the distance between the channel area edge and gate contact, and N_{cg} is the number of gate contacts per finger [7] . Capacitive coupling of the gate extension to the substrate is also considered in the above equation by using a factor 1/3. Compared to the previous works [7] [8] , Equation (4) has the second term inversely proportional to the channel area LN_{f}W_{f}, which originates from the vertical resistance elements. As the channel area decreases, this influence increases.

3. Parameter Extraction for NQS Resistances

In low-frequency operation, carriers in the channel can respond immediately to the applied terminal voltages, which correspond to charging and discharging of the gate-source capacitance C_{gs}. This is considered as quasi- static operation. On the other hand, as the operation frequency gets much higher, the channel resistance influences response time of the carriers, which is NQS operation. Although the transconductance, drain conductance and large-signal operation are influenced by the NQS effect, the influence of the small-signal gate-source admittance y_{gs} is crucial in the multi-band and wide-band LNA designs. This paper focuses on the small-signal gate-source admittance.

To estimate the NQS effect, the careful parameter extraction for MOSFET model is required. Figure 2(a) shows the small-signal equivalent circuit which includes external parasitic elements. In this work, the body is connected to the source, resulting in no body effect. R_{gsi} and R_{gdi} in Figure 2(b) give NQS effect. R_{ge} is a gate electrode resistance, R_{de} and R_{se} are series resistances of drain and source, and C_{gse} and C_{dse} are overlap capacitances between gate/source and drain/source. Extraction method separates extrinsic and intrinsic parameters from two-port parameters of the MOSFET. In the first step, the external resistances (R_{ge}, R_{de} and R_{se}) and the external capacitances (C_{gde}, C_{gse} and C_{dse}) are de-embedded from the two-port parameters of the MOSFET, using the

(a) (b)

Figure 2. (a) Small-signal equivalent circuit of MOSFET including external parasitic elements and (b) its intrinsic part.

de-embedding technique [8] . The estimation technique of the external resistances and capacitances are described later. In the second step, the equivalent circuit including only intrinsic parameters can be obtained.

To estimate the external parameters, the cold biasing (V_{GS} = V_{DS} = 0 V) is utilized. It is assumed that the intrinsic parameters except for drain-source conductance g_{ds} are not presented in cold bias. External parameters are nearly independent on V_{GS}. Thus, the Z-parameters of the MOSFET in the cold biasing can be obtained as follows:

(5)

(6)

(7)

In the cold bias condition, g_{ds} is negligibly small. Assuming it, real parts of the Z-parameters in high frequency can be approximated as

(8)

(9)

(10)

From these equations, R_{ge}, R_{de} and R_{se} can be estimated. In addition, Using Equations (5)-(10) with the same assumption of small g_{ds}, imaginary parts of the Z-parameters can be approximated as.

(11)

(12)

(13)

From these equations, C_{gse}, C_{gde} and C_{dse} can be estimated.

The intrinsic Y-parameter matrix can be obtained from the embedded Z-parameter matrix of the MOSFET model shown in Figure 2 by using the following equations.

(14)

(15)

(16)

Based on the equivalent circuit shown in Figure 2(b), the parameters of MOSFET’s intrinsic parts can be calculated from relations of real and imaginary parts of Equation (16) as following equations.

(17)

(18)

(19)

(20)

(21)

(22)

4. Verification of Gate Electrode Model and NQS Effect

In this work, instead of on-chip high-frequency S-parameter measurement, simulated small-signal S-parameters are used with a RF MOSFET model (BSIM4 with GATEMOD = 3 [25] ), which can reproduce RF and DC characteristics well with many parameters for commercial 130-nm CMOS process. This can realize cost-effective verification of device models. As narrow gate width under 3 μm has an effect of the interface resistance on the gate resistance, NMOS devices with a single finger width of 3 μm and a both-side gate connection are used in this work. The embedded Z-parameter matrix can be obtained from the simulated S-parameters of the device for the maximum frequency of 50 GHz.

The external gate resistance R_{ge} is extracted by using Equations (5)-(10), and is compared with calculated ones by using Equation (4). The results are illustrated in Figure 3. The second term of Equation (4) originates from the vertical current paths. To confirm the influence of the vertical current path in Figure 1, we calculated R_{ge} with and without the second term (solid and dotted lines in Figure 3, respectively). The values of are determined by curve fitting as 12.5 Ωμm^{2} which is reasonable value considering the reported typical values [11] [23] . From this figure, consideration of the vertical current path becomes significant for small gate finger numbers. It is more effective for short-channel devices.

Based on the extracted external parameters, NQS gate-source resistance R_{gsi} and transconductance g_{m} are extracted by using Equations (19) and (21). In this parameter extraction, to neglect high-order NQS effect [26] and delays in transconductance and drain conductance [8] , the maximum frequency is set to 6.5 GHz. Figure 4 shows the dependence of R_{gsi} on drain-source voltage V_{DS} at the gate-source overdrive voltages V and 0.8 V for various gate lengths. In saturation region (), R_{gsi} has little V_{DS} dependence.

Figure 5 shows Elmore constant κ obtained from extracted R_{gsi} and g_{m} with Equation (1) as a function of gate length. As mentioned above, κ is around 5 for L > 1 μm. For L < 1 μm, it decreases to about 3, which may originate from velocity saturation [27] . The small-signal local channel conductance in the velocity saturation region

Figure 3. Extracted and calculated values of gate resistance R_{ge} versus the number of gate figners N_{f} (L = 140 nm, W_{f} = 3 μm, both-side gate connection).

(a) (b)

Figure 4. Extracted values of NQS gate-source resistance R_{gsi} of NMOS devices with gate length L = 140; 500; 1000; 2000 and 5000 nm at gate-source overdrive voltages (a) V_{GS} − V_{TH} = 0.4 V and (b) V_{GS} − V_{TH} = 0.8 V (gate width is 120 μm (3 μm × 40 fingers), both-side gate connection).

Figure 5. Gate length dependence of extracted Elmore constants κ.

is smaller than in the non-velocity-saturation source-side region. However, the value of κ around one, as reported in previous works [8] [17] , could not be confirmed even for minimum gate length (L = 140 nm) in this work. We guess the κ for short-channel devices may have a dependence on channel-length modulation, drain- induced barrier lowering, and so on, which show significant and complicated dependence on device structure.

5. Conclusion

In this work, the gate electrode resistance of MOSFET and NQS effect are analyzed using 130-nm CMOS process. The vertical current paths between silicide layer and poly-silicon are considered in MOSFET. The vertical current paths are not effective in the devices with large channel area, but become more significant as the channel area decreases. The gate electrode resistance including vertical current paths can reproduce well the practical RF characteristics. With the scaling of CMOS technology, this effect is not considered till now in RF CMOS circuit designs, but it has a significant effect in the design of multi-band and wide-band CMOS LNAs. By careful separation of the above gate electrode resistance and the NQS effect, the intrinsic small-signal parameters were extracted. The high-accuracy analysis considering physical characteristic with the vertical elements is verified. Elmore constant of the NQS gate-source resistance (κ) about five was confirmed for the long-channel devices, while it decreases down to about three for the short-channel devices. The value of κ around one, reported in previous works, could not be confirmed even for minimum gate length in this work. The NQS effect in short-channel devices may have significant and complicated dependence on device structure. For further studies, the analyses on various processes with various device structures are more required for RF CMOS circuit designs.

Acknowledgements

This study is supported by the VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with Agilent Technologies Japan, Ltd., and Cadence Design Systems, Inc.

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Appendix

The lumped elements of MOSFET's horizontal and vertical gate resistance can be composed as like Figure 1(b). The steady state at the angular frequency ω in only the gate electrode on the channel () is considered now. Using Equation (2), the admittance of vertical terms for signal propagation length dz on the gate electrode surface is expressed as. The signal voltage and current on the gate electrode surface can be obtained by solving the following differential equations

(23)

(24)

Thus, the voltage and current can be expressed as

(25)

(26)

where is given by

(27)

The boundary conditions to obtain V_{+} and V_{−} in case of a single-side gate connection (,) gives the gate electrode impedance as. Similarly, in case of a both-side gate connection (), the gate electrode impedance can be obtained as. As a result, the gate electrode impedance is given by

(28)

where k is 1 and 1/4 for a single-side and a both-side gate connections, respectively. The approximation is valid

for. The second and third terms of Equation (28) contribute to the gate electrode resistance.