Journal of Power and Energy Engineering, 2013, 1, 1-6
http://dx.doi.org/10.4236/jpee.2013.15001 Published Online October 2013 (http://www.scirp.org/journal/jpee)
Copyright © 2013 SciRes. JPEE
New Multilevel Mixed Topology Development to Improve
Inverter Robustness for Domestic Photovoltaic
Installations
Sébastien Jacqu es, Adelp he Caldeira, Ambroise Schellmanns, Zheng Ren, Nathalie Batut
GREMAN UMR-CNRS 7347, University of Tours, 7 Avenue Marcel Dassault, 37200 Tours, France.
Email: sebastien.jacques@univ-tours.fr
Received July 2013
ABSTRACT
Multilevel inverters are well u sed in grid connected domestic p hotovoltaic applications because of their ability to gen-
erate a very good quality of waveforms, reducing switching frequency, and their low voltage stress across the power
devices. However, this kind of inverter has to be modified to both limit common-mode currents and improve the ro-
bustness of the system. This paper presents a new mixed 5-level inv erter that meets these challenges. The op erating
principle of the converter is proposed. Several experimental measurements are described to validate this new concept.
The output voltage and current and the THD of the output voltage are particularly discussed.
Keywords: Domestic PV Applications; Common Mode Currents; Decoupling Capacitances; Mixed 5-Level Inverter
1. Introduction
The global market for solar photovoltaic (PV) systems
using tran sformerless config ur a tion has been growing
over the last decade or more with an average rate from
30% to 40% per year. In particular, grid-connected PV
installations contribute significantly to this a verage growth
rate [1]. The technical performances and robustness of
inverters are key elements t hat may have a significant
impact on the generation of electricity and the profitabil-
ity of domestic grid-con nected PV systems.
PV inverters typically operate with a switching fre-
quency of about 15 kHz. As can be seen in F igure 1, this
frequency can be reflected to the DC bus and gener ate
common-mode currents which flow through the metallic
frame and the stray capacitances of the PV modules [2,3].
These parasitic capacitances are key contributors of a
resonant circuit which consists of the PV modules, the
AC filter elements and the grid impedance. The value of
these str ay capacitances, which could reach 1 50 nF∙kW−1,
depends on weather conditions, PV topology, PWM pat-
tern, the material used in the metallic frame and the pas-
sive elements of the converters [4]. The transformerless
configura tion for PV systems could result in safety prob-
lems particularly when leakage currents appear at th e
positiv e and negative PV terminals. Th e DIN VDE
0126-1-1 document specifies that the maximum leakage
ground current is equal to 300 mA [5]. Regarding do-
mestic applications, the UTE C 15-712 standa rd requires
the use of 30 mA differential circ uit breaker inside the
PV installation. However, the leakage current can in-
crease over 30 mA that lead s to the installation shutting
down. So, the limitation of common-mode currents has
become an important challenge.
NPC (Neutral Point Clamping) topologies are well-
known converter structures that are able to eliminate
common-mode currents because the middle point of the
DC source is fixed (i.e. clamped by diodes). Therefore,
no leakage current can be generated [6,7]. In symmetrical
configura tion, 5-level NPC inverter enables to signifi-
cantly improve the Total Harmonic Distortion (THD) of
the output voltage and current and decrease the voltage
constraints across the semiconductor devices in compar-
ison with the H-bridge converter topology. However, 5-
level NPC inverter requires the use of 4 decoupling ca-
pacitors, 8 power switches and 6 clamping diodes that
could considerably increase the complexity and cost-
effectiveness of the system. It is important to notice that
the electrolytic capacitors, u sed for power decoupling
between and the single-phase grid, are the main limiting
components inside the inverter. Equation (1) shows that
the operational lifetime (LOP) of the decoupling capacitor
depends on the hotspot temperature (Th). The LOP,0-pa-
rameter is the lifetime at a hotspot temperature of T0. The
∆T-parameter is the temperature increase that reduces the
lifetime by a factor of two [8].
0h
– T
(T )/DT
OP OP,0
LL 2= ×
(1 )