O. S. AHMED ET AL. 279

Table 3. All transitions between initial LPs and merged

LPs.

LP1,0 LP2,0 LP3,0

LP1 9 0 6

LP2 3 3 0

L3 P3 3 0

LP4 0 9 0

LP5 0 0 6

Ta. Node trans with dit delay m

Nonsitions E

G H

ble 4sitionfferenodels.

de tra

F

Zero-delay model 96 120 110 126

Unit-delay model 96 144 152 144

Tesit chterist

Circuit Inputs

Nodes L

count

Crit

path Me

saving

Table 5.t circuaracics.

Ps ical

gates

mory

ISCAS85-C17 5 6 10 1.7 3

7483 9 36 162 4 1.6

74157 10 15 34 4 15.5

Figure 2. 4-input combinational circuit.

consumption, under the unit-delay model assump

CMOS coba

e logic interme-

. Soudris and C. Goutis,

“An Efficient Probabilistic Method for Logic Circuits

Using Real Geedings of the In-

ternational Syd Systems ISCAS

4

tion f

sed on

or

mbinational circuits. The method is

picture concept and takes into account th

diate logic pictures that may appear due to gate delays.

The proposed method was compared with both Monte

Carlo and exhaustive simulations and applied to several

circuits: ISCAS85-C17, 7483 4-bit binary adder and

74157 quad 2-inpu t multiplexer. Th e results are identical

but with much lower complexity.

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