A. SHATNAWI, M. SHATNAWI

262

igital oscillator str

llator structures h

sh

e arith-

m

[1] M. Schanerbehe Implementation

ductures are superior in terms of the

maximum frequency when compared with the non-pipe-

lined ones. This has led to a significant enhancement of

the generated sinusoidal signal in terms of the frequency

and number of samples per cycle.

The simulation results of osciave

own that the combined digital oscillators proposed in

[10] have produced sinusoidal signals with a large num-

ber of samples in comparison with the other digital os-

cillators. This makes the combined digital oscillator

structure proposed in [10] the preferable digital oscillator

structure among all digital oscillator structures.

It is to be noted that our work is sensitive to th

etic algorithms used. Thus, if faster arithmetic algo-

rithms are proposed, new implementations for digital

oscillators should be devised.

REFERENCES

rger and S. S. Awad, “T

of a Digital Sine Wave Oscillator Using the TMS320C25:

Distortion Reduction and Applications,” IEEE Transac-

tions on Instrumentation and Measurement, Vol. 39, No.

6, 1990, pp. 870-873. doi:10.1109/19.65786

[2] M. Al-Ibrahim, S. Bataineh and A. Al-Khateeb, “Digital

Sinusoidal Oscillators with High Frequency Resolution

and Low Harmonic Distortion,” International Journal of

Electronics, Vol. 87, No. 10, 2000, pp. 1209-1218.

doi:10.1080/002072100415657

[3] A. I. Abu-El-Haija and M. M. Al-Ibrahim, “Improving

Performance of Digital Sinusoidal Oscillators by Means

of Error Feedback Circuits,” IEEE Transactions on Cir-

cuits and Systems, Vol. 33, No. 4, 1986, pp. 373-380.

doi:10.1109/TCS.1986.1085932

[4] N. J. Fliege and J. Wintermantel, “Complex Digital Os-

cillators and FSK Modulators,” IEEE Transactions on

Signal Processing, Vol. 40, No. 2, 1992, pp. 333-342.

doi:10.1109/78.124943

[5] M. M. Al-Ibrahim and A. M. Al-Khateeb, “Efficient Low

Frequency Digital Sinusoidal Oscillator,” International

Journal of Electronics, Vol. 81, No. 2, 1996, pp. 159-169.

doi:10.1080/002072196136823

[6] M. M. Al-Ibrahim and A. M. Al-Khateeb, “Digital Sinu-

soidal Oscillator with Low and Uniform Frequency

Spacing,” IEE Proceedings of Circuits, Devices and Sys-

tems, Vol. 144, No. 3, 1997, pp. 185-189.

doi:10.1049/ip-cds:19971004

[7] M. M. Al-Ibrahim and A. M. Al-Khateeb, “Extremely

Low Sensitivity Digital Sinusoidal Oscillator Structure,”

International Journal of Electronics, Vol. 85, No. 6, 1998,

pp. 755-765. doi:10.1080/002072198133806

[8] A. A. Hiasat and A. M. Al-Khateeb, “New High-Resolu-

tion Digital Sinusoidal Oscillator Structure with Ex-

tremely Low Frequency and Sensitivity,” International

Journal of Electronics, Vol. 86, No. 3, 1999, pp. 287-296.

doi:10.1080/002072199133427

[9] M. M. Al-Ibrahim (Jarrah), “A Multi Frequency Range

High Resolution and

rm-Frequency

Digital Sinusoidal Oscillator with

Uniform Frequency Spacing,” IEEE Transactions on Cir-

cuits and Systems—II: Analog and Digital Signal Proc-

essing, Vol. 48, No. 9, 2001, pp. 872-876.

[10] M. M. Al-Ibrahim, “A New Hardware-Efficient Digital

Sinusoidal Oscillator with Low- and Unifo

Spacing,” Electrical Engineering, Vol. 85, No. 5, 2003 pp.

255-260. doi:10.1007/s00202-003-0168-4

[11] M. D. Ercegovac and T. Lang, “Digital Arithmetic,” Mor-

gan Kaufmann Publishers, Burlington, 2003.

[12] C. K. Koc, “Parallel Canonical Recording,” Electronics

Letters, Vol. 32, No. 22, 1996, pp. 2063-2065.

doi:10.1049/el:19961402

[13] A. D. Booth, “A Signed Binary Multiplication T

Quarterly Journal of Mec

echnique,”

hanics and Applied Mathemat-

ics, Vol. 4, No. 2, 1951, pp. 236-240.

doi:10.1093/qjmam/4.2.236

[14] C. S. Wallace, “A Suggestion for a Fast

Transactions on Electronic

Multiplier,” IEEE

Computers, Vol. 13, No. 2,

1964, pp. 14-17. doi:10.1109/PGEC.1964.263830

[15] D. Villeger and V. G. Oklobdzija, “Evaluation of Booth

Encoding Techniques for Parallel Multiplier Implementa-

tion,” Electronics Letters, Vol. 29, No. 23, 1993, pp.

2016-2017. doi:10.1049/el:19931345

[16] V. G. Oklobdzija and D. Villeger, “Improving Multiplier

Design by Using Improved Column Compression Tree

tion and Gen-

and Optimized Final Adder in CMOS Technology,” IEEE

Transactions on Very Large Scale Integration (VLSI)

Systems, Vol. 3, No. 2, 1995, pp. 292-301.

[17] V. G. Oklobdzija, D. Villeger and S. S. Liu, “A Method

for Speed Optimized Partial Product Reduc

eration of Fast Parallel Multipliers Using an Algorithmic

Approach,” IEEE Transactions on Computers, Vol. 45,

No. 3, 1996, pp. 294-306. doi:10.1109/12.485568

[18] P. F. Stelling and V. G. Oklobdzija, “Optimal Circuits for

Parallel Multipliers,” IEEE Transactions on Computers,

Vol. 47, No. 3, 1998, pp. 273-285.

doi:10.1109/12.660163

[19] A. Weinberger and J. L. Smith, “A L

Addition,” National Bure

ogic for High-Speed

au of Standards Circulation, Vol.

Bulletin, Vol. 23, No. 8, 1981, pp.

ficiency in Parallel Multipliers Using Com-

ence, University of Adelaide, 1990.

e: A

591, 1958, pp. 3-12.

[20] A. Weinberger, “4:2 Carry-Save Adder Module,” IBM

Technical Disclosure

3811-3814.

[21] D. Villeger and V. G. Oklobdzija, “Analysis of Booth

Encoding Ef

pressors for Reduction of Partial Products,” 1993 Con-

ference Record of The Twenty-Seventh Asilomar Confer-

ence on Signals, Systems and Computers, Vol. 1, 1993,

pp. 781-784.

[22] P. J. Ashenden, “The VHDL Cookbook,” Department of

Computer Sci

[23] U. Heinkel, M. Padeffke, W. Haas, T. Buerner, H. Braisz,

T. Gentner and A. Grassmann, “The VHDL Referenc

Practical Guide to Computer-Aided Integrated Circuit

Design Including VHDL-AMS,” Wiley, Chichester, 2000.

[24] Introduction to ModelSim Simulation Software Tool.

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