** Circuits and Systems** Vol.4 No.8(2013), Article ID:41242,6 pages DOI:10.4236/cs.2013.48065

A Quadrature Oscillator Based on a New “Optimized DDCC” All-Pass Filter

^{1}Computor Imaging and Electronic Systems Group (CIEL), Research Unit (ICOS), Sfax, Tunisia

^{2}University of Sfax, National Engineering School of Sfax (ENIS), Sfax, Tunisia

^{3}Development Group in Electronics and Communications (EleCom) Laboratory (LETI), Sfax, Tunisia

Email: Achwek.bensaied@gmail.com, samir.bensalem@isecs.rnu.tn

Copyright © 2013 Achwek Ben Saied et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. In accordance of the Creative Commons Attribution License all Copyrights © 2013 are reserved for SCIRP and the owner of the intellectual property Achwek Ben Saied et al. All Copyright © 2013 are guarded by law and by SCIRP as a guardian.

Received November 13, 2013; revised December 13, 2013; accepted December 20, 2013

**Keywords:** Proposed Current Controlled Oscillators; CMOS 0.18 μm Process of TSMC; Current Conveyor; Differential Difference Current Conveyors

ABSTRACT

In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive elements grounded capacitor. This structure of filter is used to realize a quadrature oscillator. The proposed circuits employ tow optimized differential difference translinear second generation current conveyers (DDCCII). These structures are simulated using the spice simulation in the ADS software and CMOS 0.18 μm process of TSMC technology to confirm the theory. The pole frequency can be tuned in the range of [11.6 - 39.6 MHz] by a simple variation of a DC current.

1. Introduction

Differential difference current conveyors (DDCCs) are useful current-mode building blocks and many authors have demonstrated their versatility in CMOS analog circuit esign [1]. Generalized impedance converter, filter, oscillator, quadrature oscillator, floating or grounding resistor and inductance simulation are an important domain of application of DDCCs [2-4]. Indeed, the realizetion of voltage-mode (VM) first-order all-pass filters is quite recent [5]. These structures present some advantages, such as the possibility to control the frequency or the gain after integration [6-8]. DDCC-based filter or quadrature oscillator presents a good solution to avoid limitations of Surface Acoustic Wave, such as problems of integration, impedance matching, tuning, linearity, etc [3,6].

In order to get tuning parameters for the proposed structure, translinear differential difference second generation current controlled conveyor based structure seems to be the most attractive [9-11]. This DDCC gives a possibility to control the functions [5-8] characteristics by parasitic resistor at port X by means of a current source [12-14]. These DDCCs are extended in CMOS technology to realize a high frequency application such as filters, oscillators, quadrature oscillator and buffer [10,15,16]. To minimize the problem given by the passive element, floating and grounding resistor or floating and grounding capacitor or floating and grounding inductor, DDCC seems to be the most attractive [3,4,14].

This paper is organized as follows: In Section II, we present the proposed all-pass filter which uses two second generation current conveyor and two optimized differential difference current conveyors (DDCCs) and one grounded capacitor. This structure is ameliorated by replacing the grounding capacitor by CMOS Varactors. In Section III, we give the optimized DDCC implementation CMOS 0.18 μm process of TSMC technology. After this, we illustrate the simulation results of the optimized differential difference translinear second generation current conveyors (DDCCs) implemented in 0.18 μm CMOS technology. In Section IV, we illustrate the simulation results of the proposed DDCC all pass filter. In Section V, we present the CCII-based Quadrature oscillator architecture. This application using the proposed filter connected to an integrator in a closed loop. Finally, to validate theoretical analysis, the different circuits are designed and simulated using spice simulation in the ADS software.

2. The Proposed All-Pass Filter

A number of current and voltage mode all-pass filters employing the DDCC have been suggested [17]. However most of these realizations employ floating capacitors and resistors which require a large area to be implemented by MOS transistors. The proposed structure use two DDCC, two CCII and only grounded capacitor. The input of the voltage-mode (VM) all-pass filter is connected to the Y terminal (high input impedance) and its output is connected to the X terminal (low output impedance). For this reason the proposed structure doesn’t necessitate a buffer cascade with another bloc. The architecture of the filter is given in Figure 1.

The transfer function and the phase of this filter can be expressed by:

(1)

(2)

The pole frequency of the filter is calculated as:

(3)

The type of the filter gives a good solution to realize a controlled Quadrature oscillator [17]. The oscillator frequency can be adjusted by means of the value of the capacitor or the bias current of CCII_{2,3} (the value of R_{eq}). However the capacitor values are not variable after integration, for this reason we present an ameliorate structure for the filter when we replaced the grounding capacitor by CMOS Varactors or by a multiplier capacitor [18]. Figure 2 displays the architecture of the ameliorated filter.

3. The Optimized Differential Difference Translinear Current Conveyor

The DDCC is a four terminal active block. The symbol and the equivalent circuit of the the DDCC are illustrated in Figure 3.

Figure 1. The proposed all-pass filter.

Figure 2. The ameliorated all-pass filter.

Figure 3. General representation of DDCC.

The DDCC ensures two functionalities between its terminals:

• A Current follower between terminals X and Z.

• A Voltage follower between terminals X and (Y_{1} - Y_{2}).

In order to get ideal transfers, a DDCC should be characterized by low impedance on terminal X and high impedance on terminals Y_{1}, Y_{2} and Z. In this configuretion, the relation between terminal voltages and currents can be given by the following matrix:

(4)

To realize this structure it’s necessary to cascade CMOS differential voltage buffer (DVB) with a CCII. An implementation of the CMOS differential voltage buffer (DVB) and the CCII are respectively shown in Figures 4 and 5 [2-4].

A. CMOS Differential Voltage Buffer The (DVB) is shown in Figure 4 [3,4]. The input transconductance elements are realized with two differential stages (M1 and M2, M3 and M4). The high gain stage is composed of a current mirror (M5 and M6). It converts the differential current to a single-ended output current (M7). The output voltage of this amplifier can be expressed as:

(5)

where

(6)

(7)

Figure 4. CMOS differential voltage buffer.

Figure 5. Voltage DC transfer characteristic of the DVB (where Ya = Vx’ and Vy = Vy_{1} - Vy_{2}).

To determinate the optimal transistor sizes (W and L) for this structure we will use the heuristic methodology [6,7]. This strategy consists on minimizing the impedance output value, assuming that the current mirror has unity gain and closer β_{y}_{1} and β_{y}_{2} to the unity. The output resistor is calculated as:

(8)

Simulation conditions are summarized in Table 1 and the resultant optimal transistor sizes (W and L) are presented in Table 2.

The optimized CMOS differential voltage buffer was simulated with Spice simulation in the ADS software. Main obtained results are represented in Figures 5 and 6. Figure 5 displays the DC transfer characteristics of the DVB. The voltage transfer can be linear between −0.6 V and 0.6 V. Moreover, the bandwidths of output terminals are shown in Figure 6. The −3dB bandwidths of are located at 3.75 GHz.

The time-domain response of the optimized DVB is shown in Figure 7. A sine wave of 100 mV and −100 mV amplitude and 200 MHz is respectively applied as the input Y_{1} and Y_{2} to the filter. We notice that the output Waveforms are confused with the differential input Waveforms V_{y}_{1}(t) - V_{y}_{2}(t). This result confirms the good functionality of this structure.

Figure 6. Frequency response of the voltage follower Vx’/ (Vy_{1}_{ }- Vy_{2}).

Figure 7. The simulation result of voltage waveforms of Vx’ and (Vy_{1}_{ }- Vy_{2}).

Table 1. Simulation conditions.

Table 2. Optimal device sizing.

An implementation of the second-generation translinear loop based current conveyor with a positive current transfer from X to Z (CCII+) is shown in Figure 8 [7]. In Table 3 we give the different transistor size.

Table 3 shows the optimal device scaling that we get after applying the optimization approach.

The static and dynamic characteristics of the translinear configuration are summarized at Table 4.

4. Simulation Results of the Proposed All-Pass Filter

The VM all-pass filter (Figure 1) is simulated with the SPICE program using 0.18 µm TSMC CMOS technol-

Figure 8. Translinear loop MOS based implementation of CCII.

Table 3. Optimal device sizing.

Table 4. Performance characteristics of the optimized CCII with Io = 100 µA and 1.5 supply voltage.

ogy. The CMOS implementation of the DDCC+ is shown in Figure 9. The transistor aspect ratios of MOS transistor were chosen as in Tables 2 and 3 and the supply voltage was ±1.5 V. The biasing current was taken respectively as 100 µA for the DDCC and 30 µA for the CCII (R_{eq} = R_{X}_{2} + R_{X}_{3} = 1.5 KΩ). The simulation results for the magnitude and phase responses of Vout are shown in Figure 10 where we take C = 6 pF. In this figure, the pole frequency of 19MHz is obtained. The pole frequency is 19 MHz instead of 17.7 MHz owing to the effect of the parasitic impedances of the DDCC. The relative error between theoretical and simulation value is equal to 7%.

To confirm this result, the circuit is inputted with a sinusoidal signal of 19 MHz. The input and +90˚ phase shifted output (V_{out}) are shown in Figure 11. Figure 12

Figure 9. CMOS realization of the DDCC.

Figure 10. Gain and phase responses of proposed all-pass section.

Figure 11. Input and output waveforms for the circuit at 19 MHz.

shows the variability of the pole frequency of Figure 1 with the bias current I_{o}_{2,3}. The pole frequency can be controlled in the range [11.6 MHz, 36.6 MHz] by varying I_{o}_{2,3} in the range [10 µA, 200 µA].

5. Quadrature Oscillator Based on the Proposed All-Pass Filter

To illustrate the utility of the proposed first-order all-pass filter (high input and low output impedances), no buffer is required to connect it to the integrator circuit [18]), it is connected in cascade to an integrator in a closed loop [17] to construct a quadrature oscillator, as shown in Figure 13. It is seen that the proposed architecture uses three optimized CMOS DCCIIs, tow CCII’s, one floating resistor and tow grounded capacitors. The corresponding characteristic

Figure 12. Pole-frequency tuning with bias current I_{o2,3}.

Figure 13. The proposed quadrature oscillator implementation.

equation is given by:

(9)

This leads to the following oscillation condition and oscillation frequency respectively:

(10)

(11)

The confirmed performance of the quadrature oscillator can be seen in Figure 14, showing the responses of the oscillator where C_{1} = 6 pF, C_{2} = 10 pF, R = 600 Ω, and I_{o}_{2,3} = 30 µA (R_{eq} = R_{X}_{2} + R_{X}_{3} = 1.5 KΩ). The phase difference between two out puts V_{out1} and V_{out2} is 90˚ and the oscillation frequency is equal to 26 MHz (the theoretical value of the oscillation frequency is 30.5 MHz).

Figure 14. The simulated quadrature output waveforms of V_{out1} and V_{out2}.

The quadrature relationships between the generated waveforms have been verified using Lissagous figure and shown in Figure 15.

Figure 15. Lissagous figure.

6. Conclusion

In this paper, we have proposed a new design of VM first-order all-pass filter. In order to get high performances of the filter, a translinear DCCII and CCII structures are optimized in 0.18 µm CMOS process of TSMC. The theoretical analysis is verified with the SPICE simulation program. The application example as the quadrature oscillator is included. It shows good usability of the proposed all-pass filter.

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