lass="cs_fig_con">Figure 2, and can be derived using the equivalent circuit shown in Figure 6.
The circuit can be characterized by the Equations (14) and (15).
By eliminating vs1 in (14) and (15), gYout21 is expressed as
Then gYout2 =1/gZout2 is expressed as
By definition, A1 corresponds to the voltage gain vs2o/vg1, where vs2o is the vs2 node voltage when open, and can be derived using the equivalent circuit shown in Figure 7. The circuit can be characterized by the Equations (18) and (19).
Figure 6. AC equivalent circuit to find gZout2.
Figure 7. AC equivalent circuit to find A1.
By eliminating vs1 in (18) and (19), we get
gZout1 corresponds to the impedance seen to the left of the vo node with vs2 = 0 in Figure 2. Since gm2vs2 and (Cgs2 + Cjs2) do not function when vs2 = 0, gYout1 = 1/gZout1 is simply expressed as
A2 corresponds to the voltage gain voo/vs2, where voo is the vo node voltage when open, and A2 derivation can be done in the similar fashion to the one for A1 derivation. The resulting A2 is expressed as
In Figure 2, the available input power Pi, which is supplied to the LNA when impedance matched, is defined as
The maximum output power Po, which is supplied to the resistive load Rso when impedance matched, is expressed as
where vo and vout are defined in Figure 2, and Rp is the transformed parallel resistance of Rso, which is already defined relating (1).
Then the available power gain G is expressed as
where Av1, Av2, and Av3 can be easily derived from Figure 5 as follows.
4. Automatic Sizing Algorithm
Figure 8 shows the automatic sizing algorithm developed in this work. The inputs to the algorithm include design and process specifications, and the outputs include synthesized design variable values are for RDB, W, nfb, Ls, Lg, Ci, R1, L1, Co. Here, we explain the procedures from top to bottom in accordance with each step, which is explicitly indicated in Figure 8.
4.1. 1st Step: Entering Design and Process Specifications
The 1st step in the automatic sizing is to enter the design
Figure 8. Automatic sizing algorithm.
and process specifications. The design specifications include the operating frequency f, the input output terminations Rsi and Rso, the supply current IDD, the desired power gain Gain_design. Instead of IDD, the power consumption PWR and the supply voltage VDD can be entered to calculate IDD by PWR/VDD. The process specifications include the transistor channel length L, the transistor channel width per finger WF, and the maximum finger number nf_max defined for one unit of transistors.
4.2. 2nd Step: Calculation of Optimum Transistor Width
The next step is to calculate the transistor channel width W for optimum noise performance. The width for optimum noise performance is usually too large for practical use, and therefore the power-constrained noise optimization (PCNO) device width WoptP  is adopted as W in this work. WoptP is calculated according to the last rough equation in (29).
As shown in (29), WoptP increases continuously as the frequency decreases. Therefore it may be necessary to define a maximum value for W considering lower frequency design. We suggest to limit W below 1000 μm.
If WF and nf_max are defined, the finger number nf is first calculated as W/WF, and the number of the maximum-fingered units m is calculated as the integer value of nf/nf_max, and the residual finger number nf_residue is determined as the residue to give an information for the transistor layout. Then the final W is determined by W = WF × (m × nf_max + nf_residue). We note that WF and nf_max are usually defined in most of recent processes.
4.3. 3rd Step: Calculation of Bias Circuit Design Variables and Getting DC Operating Point Information
The next step is to determine the bias circuit variable values and to get the dc operating point information.
The finger number for the bias transistor nfb and the drain bias resistance RDB in Figure 1 should be determined. By limiting the bias circuit current around 100 μA, for example, we can determine nfb by nfb = (100 μA/IDD) × nf. For the decoupling resistor RB, we can simply use 5 kΩ, which is a reasonable value.
The next procedure is to determine RDB, which, however, is very difficult to determine by calculation. Since IDD is sensitive to the value of RDB, it should be manually determined to give the specified IDD value by dc circuit simulations. This procedure is one obstacle against full design automation in this work. However, it is an essential procedure since it provides the accurate operating point information to proceed with the remaining part of the design automation. The needed operating point information include the values of gm, gds, Cgs, Csg, Cgd, Cdg, Cds, Csd, Cjs, and Cjd of M1 and M2 in Figure 1, which should be imported into the automatic sizing algorithm.
4.4. 4th Step: Iterations to Determine Design Variable Values
There are three main iteration loops in the automatic sizing algorithm as shown in Figure 8. The 1st loop finds Gmax, which corresponds to the case with the upper limit of R1, which is chosen arbitrarily large enough as 10 kΩ in this work. To find Gmax, we need to find all the design variable values for the Gmax case simultaneously. Iteration is needed since the input and output matching designs affect each other. The 2nd loop finds Gmin, which corresponds to the case with the lower limit of R1, which is arbitrarily chosen small as 40 Ω in this work to allow a larger allowable gain range. This iteration is also needed for the same reason explained for the Gmax case. The 3rd loop finds the proper R1 value for the desired gain Gain_ design by the bisection method, which lies within the lower and upper boundaries Gmin and Gmax, and its inner loop finds the corresponding design variable values for the present gain value during iteration similarly as in the 1st and 2nd iteration loops.
4.4.1. Iterations to Solve for the Gmax Case
As explained above, Zin1 is affected by output matching design, and Zout is affected by input matching design. Therefore we need some iteration to determine Ls. Since Zin2 is affected by Zo, which is unknown yet, we need an initial guess for Zo to find the 1st Ls value. As shown in Figure 8, an initial guess for ZoL = Zo//(1/sCL) is given as 50/g·m2, which is shown to be large enough for all possible situations in the procedure, to solve for Zin2 by (5).
The impedance seen at the gate of M1 is equal to Zin1, which is derived in (9). By setting the real part of Zin1 Re(Zin1) equal to Rsi for input impedance matching, we can find Ls. However this equation Re(Zin1) = Rsi is too complicated to get the solution directly with the other present design variables values given, and therefore Ls is solicited numerically within the lower and upper boundaries of 0.1 nH and 5 nH. We use the bisection method for this purpose.
The next procedure is to calculate Lg and Ci, which nullify the imaginary part of Zin1 Im(Zin1) in Figure 2. Zin1 is usually capacitive to give a negative value for Im(Zin1), and therefore Lg can be calculated using the equation Im(Zin1) – 1/(ωCi) + ωLg = 0, where Ci is simply a large dc blocking capacitor. We first calculate Lg1, which nullifies Im(Zin1) using Im(Zin1) + ωLg1 = 0. Although Ci is larger the better, considering the layout size, 1/(ωCi) = ωLg1/10 is used to determine Ci. Lg is then recalculated using Im(Zin1) – 1/(ωCi) + ωLg = 0.
Depending on to the operating frequency and the desired gain, Zin1 may happen to be inductive, or this situation can happen in the middle of the iterations. For this case, a nominal single bond wire inductance of 1 nH is assumed for Lg and Im(Zin1) – 1/ωCi + ωLg = 0 is used to calculate the required Ci value.
In the next procedure, the design variables L1 and Co are determined using the equations Re(Zout) = Rso and Im(Zout) = 0 for output impedance matching to Rso, where Re(Zout) is the real part of Zout expressed in (13).
If we let Zout1 in (12) equal to A + jB, the real and imaginary parts of Zout1//jωL1 in (13) are expressed as
Then by letting Re(Zout) = Re(Zout1//jωL1) = Rso, L1 is expressed as
By letting Im(Zout) = Im(Zout1//jωL1) – 1/(ωCo) = 0, Co is expressed as
Using (31) and (32), L1 and Co can be simply calculated.
Now the 1st set of the design variable values are ready to update ZoL and the remaining iterations are performed to find the final design variable values for the Gmax case. It was found that the iteration number for this loop should be larger than 10.
Right after the iteration loop, A1, gZout2, A2, and gZout1 are calculated using (20), (17), (22), and (21), respectively, and Gmax is calculated using (25).
If the Gmax value is smaller than the desired gain, the routine gives a warning and stops.
4.4.2. Iterations to Solve for the Gmin Case
The 2nd loop finds the design variable values for the Gmin case. The same iteration as above with the last ZoL value as an initial guess is performed to find Gmin using (25) again.
4.4.3. Iterations to Solve for the Gain_Design Case
The 3rd loop finds the proper R1 value for the desired gain Gain_design using the bisection method while the inner loop finds the corresponding design variable values for the present gain value. This inner iteration loop is exactly same as the 1st and 2nd loops. After all the design variables are determined for the present gain value, the gain is calculated using (25) again. If the calculated gain is equal to Gain_design within the allowed tolerance, the calculation stops to output the final set of the design variable values, which include W, nf, m, nf_residue, nfb, Ls, Lg, Ci, R1, L1, and Co.
The automatic sizing algorithm explained in Section 4 was coded using Matlab (Version 220.127.116.119) assuming usage of a 90 nm commercial CMOS process. The design variable sets for seven different operating frequencies ranging from 0.7 GHz to 5 GHz were synthesized, and verifications were done by one-time Spectre circuit simulations with the corresponding BSIM4.5.0 MOSFET model  for the assumed process.
The design specifications include ID = 5 mA, VDD = 1.2 V, Gain_design = 21 dB, and Rsi = Rso = 50 Ω. The process specifications include L = 75 nm, WF = 3 μm, and nf_max = 64, where 75 nm for L is the effective channel length in this process. The maximum transistor width was set as Wmax = nf_max × m × WF = 64 × 5 × 3 μm = 960 μm, which is below 1000 μm as we suggested.
As examples of the verifications, Figures 9 and 10 show the simulated LNA characteristics without any tuning for the operating frequency of 1 GHz and 5 GHz, respectively, when the corresponding sets of the design variable values obtained using the automatic sizing algorithm are used for the simulations. The synthesized design variable values are as follows;
For 1 GHz design, RDB = 12.7 kΩ, W = 960 μm (m = 5, nf_residue = 0), nfb = 6, Ls = 1.382 nH, Lg = 19.557 nH, Ci = 14.25 pF, R1 = 497.1 Ω, L1 = 11.904 nH, Co = 1.447 pF.
For 5 GHz design, RDB = 5.96 kΩ, W = 231 μm (m = 1, nf_residue = 13), nfb = 2, Ls = 0.5383 nH, Lg = 2.690 nH, Ci = 4.142 pF, R1 = 1.752 kΩ, L1 = 2.813 nH, Co = 0.190 pF.
Table 1 summarizes the simulated results of the seven designs, which reside in the frequency range, where the automatic sizing program could provide the design variable set for Gain_design of 21 dB. Notice that, for the operating frequencies below 1 GHz, the synthesized W values are restricted to below 960 μm, which is equal to the value for Wmax.
In Table 1, we can see that the input and output matchings (S11 and S22) are pretty good for all the designs, and the noise figure is pretty close to the noise figure minimum, which demonstrates the adequacy of the designs.
We note that power gain values are about the same with S21 values. The S21 values in Table 1 are smaller than the desired gain of 21 dB. This seems to be caused by neglecting gmb, Cgb, Rs, Rd, Rg, and Rsub in the equivalent circuit in Figure 2. However we believe that the result is pretty good for the first-cut quick design.
Figure 9. Simulated (a) s parameter and (b) noise characteristics for f = 1 GHz: S21 = 20.31 dB, NF = 0.660 dB, NFmin = 0.585, S11 = –23.6 dB, S22 = –23.0 dB.
Figure 10. Simulated s parameters for f = 5 GHz: S21 = 17.16 dB, S11 = –16.9 dB, S22 = –34.8 dB.
Table 2 summarizes the synthesized available gain ranges with the corresponding R1 values for each design. We can see that a wide range of power gain can be obtained by varying the R1 values as expected.
The analytical expressions for the principle parameters
Table 1. Simulation summary for the desired gain Gain_ design of 21 dB.
Table 2. Synthesis summary for the available gain ranges with the corresponding R1 values.
were derived using the ac equivalent circuit of the singleended narrow-band cascode CMOS LNA adopting the inductive source degeneration. Based on the expressions, the automatic sizing algorithm was developed by adopting the power-constrained noise optimization criteria. The algorithm was coded using Matlab, and could provide a set of design variable values within seconds. One-time Spectre simulations without any tuning assuming usage of a commercial 90 nm CMOS process were performed to confirm that the automatic sizing program can synthesize the aimed first-cut design with a reasonable accuracy for the frequency range reaching up to 5GHz.
This work showed in detail how the accurate automatic sizing can be done in an analytical approach. The approach can be applied to a common source LNA more easily since the derivation of principal parameters will be simpler with a fewer gain stages. It can be also applied to a differential LNA easily since the derivation will be basically same. The approach seems applicable to more complicated designs even though the derivation procedures will contain enhanced complexity.
The automatic sizing program may be utilized efficiently for additional tuning purpose. For example, after examining the first-cut synthesis result with verifying circuit simulations, a smaller value for WM2 compared to the synthesized one for WM1 can be entered into the automatic sizing program to obtain another design variable set for better linearity.
*This work was supported by 2011 Hongik University Research Fund (sponsors).