the outside of the chip. The chip used is a Ball Grid Array chip, and

Figure 6. Pin locations on PLANAHEAD.

Figure 7. VHDL design flow chart [10] .

Figure 8. VHDL codes for stepper motor on FPGA.

pins are located with a letter for the column and a number for the row. In this design we are using 16 pins, but the FPGA has many more available.

There is one special pin, the clk50M pin, which connects to a 50 MHz clock on the FPGA development board. It is this clock signal that co-ordinates all activities on the FPGA. The period of this signal should be specified, so that the tools can make sure that all of the design’s logic functions correctly at this speed (as the design is limited by the switching speed of the FPGA’s logic and the speed at which signals propagate across the chip). This design has three internal signals, and that also act as registers (they “hold” values). The “coils” is initialized to “0011” as it will be connected to the output of the design that powers the stepper motor, and coils A and B will be initially powered. The sizes of these signals have been carefully chosen = coils has to hold the four outputs for the stepper motor, count has to hold number to 400,000 and step count has to hold the position to be indicated on the eight LEDs.

Figure 9 shows RTL schematic and Figures 10-14 shows simulation results of the VHDL code. The VHDL code was written and simulated in XILINX ISE 14.7i [9] .

Figure 9. RTL schematic.

Figure 10. Stepper motor waveform.

Figure 11. Stepper motor implementation hardware co-simulation using FPGA successful.

Figure 12. Logic schematic.

Figure 9 shows the RTL Schematic output simulation of the implementation on the Stepper Motor on FPGA.

Figure 10 displays the Stepper Motor waveform showing constraints as applied to the FPGA such as, input and output LEDs, the phases on the Motor, Motor driver and the clock time application.

Figure 11 shows the successful Hardware Co-simulation of FPGA thereby generating the bit file that was downloaded to power on the Stepper without being connected to the computer system (Stepper Motor on stand-alone operation).

Figure 12 shows the logic Schematic that displays the gates, slices that were used for the implementation.

Figure 13 and Figure 14 show the implementation behavioral checks and the device utilization summary

Figure 13. ISE behavioral check.

Figure 14. FPGA utilization summary.

that shows the amount of resources usage for the Stepper Motor implementation using FPGA. The design has been compiled down into a “.bit” file that is used to program the FPGA, and the tools provide a usage report that shows what physical resources have been consumed. In this case we use 34 of 4656 logic slices, not even 1% of the chip: this shows how effective and less resource usage is been achieve when implemented with FPGA. Below are some other benefits of using FPGA in this Stepper Motor implementation [11] .

1) Performance―The hardware parallelism nature of FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle. Controlling inputs and outputs (I/O) at the hardware level provides faster response times and specialized functionality to closely match application requirements. This design is then compiled down into a “.bit” file that is used to program the FPGA. The tools provide a usage report that shows what physical resources have been consumed. In this case we use 34 of 4656 logic slices. Not even 1% of the chip. This again evaluates and validates the parallelism nature of FPGA which was equally achieved during our design due to small amount of resources used on the FPGA and the execution time is faster.

2) Reliability―Processor-based systems often involve several layers of concept to help schedule tasks and share resources among multiple processes. For any given processor core, only one instruction can execute at a time, and processor-based systems are continually at risk of time-critical tasks preempting one another. Because FPGAs do not use OSs, it minimizes reliability concerns with true parallel execution and deterministic hardware dedicated to every task. This was proven when all our codes instructed were executed using VHDL at the same time on the FPGA.

3) Long-term maintenance―As earlier discussed, FPGA chips are field-upgradable and do not require the time and expense involved with ASIC redesign. Due to reconfigurable nature of FPGA chips, it can keep up with future modifications that might be necessary. As a product or system matures, you can make functional enhancements without spending time redesigning hardware or modifying the board layout. During our design, we changed the configuration many times so as to drive our stepper Motor and do not incur any additional cost due to its programmability nature.

4) Cost―The nonrecurring engineering (NRE) expense of custom ASIC design far exceeds that of FPGA- based hardware solutions. With FPGA, it means that you have no fabrication costs or long lead times for assembly. This is because system requirements often change over time, the cost of making incremental changes to FPGA designs is negligible when compared to the large expense of re-designing an ASIC. In our design and implementation, the cost of the SPARTAN 3E FPGA Board is really small as compared to other processors like dSPACE in implementation of the same project.

5. Conclusion

The result has verified an easy way to design and implement a Stepper Motor using FPGA which equally guarantees an effective speed control with less resources usage. Due to the system architecture and its parallelism nature, one FPGA can drive more than one motor without increasing the processing time. The algorithm implemented on FPGA allows a substantial decrease of the equivalent processing time develop by different velocity controller. The Stepper Speed control is achieved using VHDL code. This fast prototype and implementation of Stepper Motor proves the effectiveness and programmability features of FPGA in the industrial at large.

Cite this paper

Warsame H. Ali,Emmanuel S. Kolawole,Pamela Obiomon,John H. Fuller,Shukri Ali,Penrose Cofie, (2016) Rapid Prototype with Field Gate (A Design and Implementation of Stepper Motor Using FPGA). Circuits and Systems,07,1392-1403. doi: 10.4236/cs.2016.78122


  1. 1. Matthew Grant (2005) Quick Start for Beginners to Drive a Stepper Motor. Freescale Semiconductor, Inc., Rev. 1, pp. 1-16, June.

  2. 2. Chen, C.S. (1982) Microcomputer Speed Control of Stepper Motor. IEEE Control Systems Magazine, 2, 17-20.

  3. 3. Johnson, M.I. and Subramanyan, G. (1997) A Parallel Port Interface Circuit for Computer Control Applications Involving Multiple Stepper Motors. IEEE Circuits and Systems, 2, 889-992.

  4. 4. Kuo, B.C. (1974) Theory and Application of Step Motor. West Publishing, Mumbai.

  5. 5. (2011) Diigiillentt Nexys 2 Board Reference Manual. “Digilent Xilinx”, Revision: July 11.

  6. 6. Monmasson, E., et al. (2011) FPGAs in Industrial Control Applications. IEEE Transactions on Industrial Informatics, 7, 224-243.

  7. 7. Palani (2009) Control System Engineering. 2nd Edition, McGraw-Hill, New York.

  8. 8. Perry, D. (2003) VHDL. 3rd Edition, McGraw-Hill, New York.

  9. 9. Andrew, R. (1995) VHDL for Logic Synthesis: An Introduction Guide for Archiving Design Requirements. McGraw- Hill, New York.

  10. 10. Chang, K.C. (1999) Digital Systems Design with VHDL and Synthesis. 1st Edition, an Integrated Approach.

  11. 11. Kolawole, E., Ali, W., Cofie, P., Fuller, J., Tolliver, C. and Obiomon, P. (2015) Design and Implementation of Low- Pass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filter Using FPGA. Circuits and Systems, 6, 30-48.

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