ABSTRACT

Threshold voltage (V_TH) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V_TH value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of V_TH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent V_TH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.

Keywords:

Threshold Voltage, Constant Current Source Technique, Linear Extrapolation Technique, Threshold Voltage Estimation Techniques, Short Channel Effects, Drift Diffusion Model, Resistive Load Inverter, Noise Margin Analysis

1. Introduction

Incessant abridging of IC technology, together with precision of V_TH control techniques and reduction in SCE, is asserting the V_TH to very low values. For proper operation of MOSFET, we need to evaluate exact threshold voltage (V_TH). Perfectly appraised V_TH is required to provide proper gate control over device channel conduction (see Figure 1). The tens of millivolts miscalculation cannot be neglected as it can prompt serious errors in circuit functionality. Especially for robust nano-scale design of analog circuits with high speed operation, precise valuation of V_TH is essential to illustrate the exact device behaviour [1] [2] [3] [4] . Device matching also depends on the estimated V_TH values. V_TH is frequently used for accessing and predicting device performance. It is also commonly used to check the inconsistency due to manufacturing process technological parameter fluctuations. Other applications of V_TH can be listed as to evaluate reliability factors such as radiation damage, hot carrier, stress, temperature instability, ageing degradation etc.

The threshold voltage parameter is largely extracted directly from the transfer characteristics of the device. There is no critical point in the I_D-V_GS curve that can be recognized as threshold point due to sub-threshold leakage current. This creates vagueness in V_TH estimation. The weak inversion region shows exponential deviations while strong inversion shows linear/quadratic deviations. However, the V_TH is identified amid weak and strong inversion transition region [5] [6] . V_TH also depends on several device parameters (Gate width, Gate Overlap, Gate length, biased bulk, temperature etc.) and process technology limitations (Cox, tox, doping concentration (NA) etc.) [7] [8] . This makes V_TH estimation more challenging.

In consideration to the above, this paper presents the study and analysis of numerous V_TH extraction methods at various sub 45-nm technology node. The outcomes of the analysis are implemented on a simple resistive load inverter for computing noise margins to infer the performance of various threshold voltage extraction methods at sub 45-nm technology node.

Rest of the paper is organized as follows. Section 2 categorizes several threshold voltage extraction methods on the basis of their assessment methodology. Section 3 to Section 8 discuss and evaluate the various mentioned threshold voltage extraction methods at 10-nm technology node and other sub 45-nm technology nodes. Further, Section 9 presents the tabulated compiled simulation results, comparison and discussion for various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented in Section 10. Finally, concluding remarks

are conferred in Section 11.

2. Threshold Voltage Estimation Techniques

Ideally, V_TH of a device is the critical gate voltage below which the drain to source current (I_D) is zero, But practically, sub-threshold leakage current exists for V_GS below V_TH. As the drain current doesn’t drop abruptly to zero and hence, it becomes challenging to precisely determine the critical point at which switching of I_D takes place. Due to this reason, several procedures presented in literature use diverse descriptions to extract the V_TH of the MOSFET but still has a scope for improvement to correctly evaluate V_TH [9] [10] . This paper revisits V_TH extraction techniques and examines these for simplified square-sized NMOS device at 10-nm technology node. For precise evaluation of the methods, the process is reiterated in similar conditions on other sub 45-nm technology nodes [11] [12] .

For simplicity, the threshold extraction methods have been categorized into six main groups on the basis of their assessment methodology as:

1) I_D based extraction methods;

2) Derivative of I_D based extraction methods;

3) Integral of I_D based extraction methods;

4) Self-extraction methods;

5) Deviation based extraction methods;

6) Hybrid extraction methods.

It is considered that the threshold voltage changes with the change in the operating region of the MOSFET specifically in linear/ triode region and saturation region. Distinctive efforts are made to accurately calculate the V_TH in both the operating regions [13] [14] [15] . Hence the corresponding respective values of V_TH are evaluated as V_LIN and V_TSAT for all the discoursed methods on our test device. Figure 1 shows the basic biasing settings for n-channel MOSFET. The test device considered is a square-sized uniformly doped bulk driven n-channel nano-MOSFET with 10-nm channel length. The source and drain regions are laterally identical with gradual doping characteristics. Special effects were considered to extract the realistic output of the device. Figure 2 represents the transfer characteristics of our test device.

3. ID Based Extraction Methods

These methods use the drain current (I_D) directly in the extraction method of threshold voltage. Some common methods listed underneath are briefly discussed below.

3.1. Constant Current Source (CCM) Method

This method determines V_TH as the gate voltage for an arbitrary critical drain current (I_DCRITICAL) value [16] [17] . To estimate the V_TH using this method, I_D versus V_GS graph is plotted on a semi-logarithmic scale for two extreme values of V_DS i.e. high biased and low biased. For our test device, we considered V_DS = 0.9 V and V_DS = 0.1 V respectively. The I_DCRITICAL is technology reliant, generally considered as (0.1 μA) × (W/L), where W and L are the gate width and gate length.

(1)

I_DCRITICAL referred in Equation (1) is designated such that V_TH is on the transition point of linear-sub-threshold region of the device [11] [18] [19] .

Implementation of CCM on Test Device

The technique was implemented on our test device square-sized NMOS with 10-nm technology node and was repeated in similar conditions on other sub 45-nm technology nodes. Figure 3 represents the simulated results and extraction output (V_TLIN and V_TSAT) using CCM on our test device.

The outcome of the results was as follows:

@

@.

3.2. Drift-Diffusion Equality (DDE) Method

Diffusion current governs the total current in sub-threshold region whereas drift current dominates in strong inversion region. This DDEM process states that by applying low drain voltage (V_DS ≈ 0.1 V), the threshold voltage is the distinctive gate voltage at which the condition I_DRIFT = I_DIFFUSION holds true [20] [21] . Hence, statistically we can represent the threshold voltage value as:

(2)

where I_Drift and I_Diffusion represent the drift current and diffusion current respectively.

Implementation of DDEM on Test Device

The technique was implemented on the test device.

The outcome of the result was as follows:

@.

The DDEM process has the restriction of low biased V_DS = 0.1 V. Since the device is always made to operate in linear region, hence the saturation region threshold voltage V_TSAT could not be calculated. Figure 4 shows the simulated results of our test device for I_DRIFT and I_DIFFUSION with the variation in V_GS to extract the threshold voltage.

4. Derivative of ID Based Methods

These methods use the derivative or the higher order derivate of the drain current value in the extraction method of threshold voltage. Fundamental V_TH extraction methods using this respective technique are briefly discussed below.

4.1. Linear Extrapolation (LEM) Technique

In this LEM technique, we determine the V_TH of the transistor using transconductance (g_m) and I_DS-V_GS curve. The g_m is defined as the derivative (slope) of I_D-V_GS relationship. The extreme g_m obtained on the I_D-V_GS characteristic curve is used to extrapolate the gate voltage (V_GS) as shown in Figure 5. The attained V_GS is extracted V_TH for the given conditions. The I_D for linear region is associated with V_GS as:

(3)

This LEM process provides clear steps for V_TH assessment but it is partial to linear region of operation i.e. for low values of V_DS. Maximum g_m point is not obtainable for higher values of V_DS. Furthermore, the DIBL effect also comes into picture for higher V_DS and diminishes effective V_TH values. Apart from these issues, this method also lacks to determine a constant V_TH as dissimilar methods used for attaining maximum g_m values. g_m also depends on SCEs such as velocity saturation, overlap variations, extrinsic resistance, channel length modulation and so on. This reliance of g_m and critical point of maximum g_m is tough to accurately model. Henceforth, this produces loopholes in this process to precisely evaluate the V_TH.

Implementation of LEM on Test Device

The technique was implemented on the test device.

The outcome of the result was as follows:

@.

As described above, the Maximum g_m is not obtainable for higher values of V_DS. Hence special efforts were made to calculate V_TSAT using this method. Figure 5 shows the transfer characteristics of the test device and the g_m variation with the variation in V_GS at constant V_DS = 0.1 V.

4.2. Quadratic Extrapolation (QEM) Method

Technique named Quadratic Extrapolation Method (QEM) is also called as “Linear Extrapolation in Saturation Region”. It is used to calculate threshold voltage using LEM in saturation region (V_TSAT). As mentioned in LEM, the I_D for linear region is proportional to (V_GS − V_TH). Similarly, I_D in saturation region is proportional to (V_GS − V_TH)² as shown in Equation (4):

(4)

Hence V_TSAT can be extracted by extrapolating the curve versus V_GS at the inflexion point of the curve as shown in Figure 6.

Implementation of QEM on Test Device

The technique was implemented on the test device.

The outcome of the result was as follows:

@.

4.3. Second-Derivative (SD) Method

The second-derivative method (SDM), formerly entitled as transconductance change method [21] [22] , was developed to avoid dependence on series resistances. It evaluates V_TH as the V_GS value at which the derivative of the transconductance (i.e.,

) is a maximum. To intricate the logic, it uses the ideal case of a simple Level = 1 MOSFET SPICE model, where I_D = 0 for V_G < V_T, and I_D is directly proportional to V_G for V_G > V_T. With these suppositions, dI_D/dV_G becomes a step function, which is zero for V_G < V_T and is a positive constant for V_G > V_T. Therefore,

will go to infinity exactly at V_G = V_T. Such a simple assumption is apparently not true in a real device, and thus will not turn out to be infinite at V_T. However, it will exhibit a maximum value at V_GS = V_TH. Figure 7 shows the SDM output waveform of the test device for V_TLIN extraction at constant V_DS = 0.1 V.

The execution of this SDM process in the linear region is extremely sensitive to

measurement error and noise, as the second derivative amounts to applying a high-pass filter to the measurement [23] .

Implementation of SDM on Test Device

The technique was implemented on the test device. The process was widely affected by noise. Special possessions of filtration and smoothening of curve were considered to extract the correct output as shown in Figure 8.

The outcome of the result was as follows:

at

at.

4.4. Third-Derivative (TD) Method

In this TDM process, it has been proposed that the V_TH can be extracted from the value

of V_GS at which the third derivative of the current I_D (i.e.,) has a maximum value [24] . Conversely, the maxima and minima of the third derivative always fall to the left and right of the second derivative maxima, which is located at d³I_D/dV_GS³. Figure 9 clearly illustrates this fact. Therefore, the third derivative technique is evidently incompatible with the broadly used second derivative method.

Figure 9 and Figure 10 present the application of this TDM process to the 10-nm technology node test device in the linear and saturation regions, at drain voltages of 0.1 V and 0.9 V, respectively. It is clear from these figures that the TDM technique is extremely affected by tentative noisy data. Though investigational noise could be diminished by numerical flattening techniques or by fitting the semi-empiric models, the extracted V_TH value would still be irreconcilable with that extracted by the SD method.

Implementation of TDM on Test Device

The technique was implemented on the test device. The method was vastly affected by the investigational noise. Hence it was challenging to extract the threshold values. Special properties of smoothening and filtration of the curve were considered to extract the correct output. Even after high considerations, it was observed that V_TLIN value was lower than V_TSAT value which is commonly unusual.

The outcome of the result was as follows:

at

at.

4.5. Ghibaudo Method/Current-to-Square-Root-of-Transconductance Ratio (CsrTR) Method

The CsrTR method formerly called as Ghibaudo Method (GM) was developed to dodge the extracted V_TH value dependence on mobility degradation and parasitic series resistance [25] [26] [27] . The ratio of the drain current to the square root of the transconductance, in the linear region, is given by Equation (5) as:

(5)

The GM technique, also occasionally called as ‘‘the modified Y function method’’, has been freshly enhanced for application to contemporary devices using a more universal mobility degradation model.

The V_TH is extracted from the intercept of the GM versus V_GS linear fit. Figure 11 shows the results of applying this method to the present test device in the linear region. As can be witnessed, it is not very clear in the method from where to linearly extrapolate to find the V_GS axis intercept. It does not evidently show the supposedly expected linear behavior. Therefore, the linear extrapolation shown in Figure 11 is only a guess, amidst the evident non-linearity present.

Implementation of Ghibaudo Method (GM) on Test Device

The technique was implemented on the test device. Non-linearity in the curve caused difficulties in extrapolation process to estimate the required values. Figure 12 shows the results of applying this method to the present test device in the saturation region.

The outcome of the result was as follows:

at

at.

4.6. Transconductance to Current Ratio (TCR) Method

This method is based on calculating TCR as the ratio of transconductance to the drain current as described in Equation (6) [28] [29] :

(6)

It states that the threshold voltage can be determined as the value of V_GS where TCR presents its maximum negative slope i.e. V_GS corresponding to the minimum value of curve dTCR/dV_GS. However, considering TCR by itself significantly increases random tentative noise, specifically in weak inversion.

Implementation of TCR Method on Test Device

The technique was implemented on the test device. The method was highly affected by the investigational noise as seen in Figure 13 and Figure 14 for extraction of V_TLIN

and V_TSAT respectively. Hence it was challenging to extract the threshold values. Filtration and smoothening of the curve like properties were applied to extract the correct output. Even after high considerations, it was observed that V_TLIN value was lower than V_TSAT value which is generally unusual.

The outcome of the result was as follows:

at

at.

5. Integral of ID Based Methods

These methods use the integral of the drain current value in the extraction method of threshold voltage. Prevalent V_TH extraction methods using this technique are briefly discussed below [30] [31] .

5.1. Transition Method

This TM technique was stimulated by the properties of the integral difference function D(V,I), which had been formerly defined for two-terminal device as [32] :

(7)

As shown in Equation (7), this function presents the advantageous features of eradicating the effect of any linear element (resistance) coupled in series with the device. To extract V_TH, the drain current is constantly measured from below the expected value of V_TH versus V_GS with a small constant drain voltage (V_DS ≈ 100 mV). Subsequently, the succeeding function TM is numerically calculated from the measured data:

(8)

where V_G0 represents the lower limit of integration analogous to a gate voltage well below threshold in Equation (8). Usually chosen V_G0 = 0. The logic of the method is based on the ideal case of a MOSFET, piecewise modelled as: I_D = I_LEAKAGE for V_GS < V_TH and I_D is proportional to V_GS for V_GS > V_TH. Using the previous streamlining supposition, we observe that:

1) Function TM presents a discontinuity at V_TH;

2) TM = −V_GS for V_GS < V_TH; and

3) TM = +V_TH for V_GS > V_TH.

Since for a real device such simplifying conventions are apparently not precisely true, function TM will present an extreme value due to the mobility degradation and its value will be close to V_TH.

A plot of TM versus V_GS or ln(I_D) should result in a straight line below threshold, where the current is dominated by diffusion and is principally exponential. As soon as V_GS = V_TH, the function TM should vitiate due to mobility degradation. The specified logic accords with the test device as shown in Figure 15. Hence the maximum of TM approaches the V_TH value of the device. The shape of the curve is swayed by the parasitic resistance and mobility degradation effects, but not significantly its maxima, lest those effects are exceedingly prominent. Hence, the parasitic series resistance consequence is not totally eradicated since a MOSFET is not a two-terminal device with node current as I_D and node voltage as V_GS. Figure 16 represents the TM function output curve versus V_GS to extract V_TSAT for V_DS = 0.9 V.

Implementation of TM Process on Test Device

The technique was implemented on the test device. Smooth curves were obtained. Hence it was easy to extract the threshold values. The V_TLIN value and V_TSAT value can also be extracted through the TM versus I_D curve using the same procedure. On implementation of the mentioned logic, we got the same agreeing values of the threshold voltages.

The outcome of the result was as follows:

at

at.

5.2. Normalized Mutual Integral Difference Method (NMID)

The NMID method was initially developed by He and co-workers in 2002 and it was also stimulated by the integral difference function NMID [31] , but in this case normalized by product I_DV_GS as shown in Equation (9):

(9)

Consequently, a plot of NMID versus V_GS will characterize a maxima at V_GS = V_TH. Figure 17 exemplifies the claim of this method to the test device. Notice that the site of the maxima is autonomous of the constant term ‘‘1’’ which may be removed from Equation (11). A downside of this method is that the maximum of the curve is positioned in a wide region. Hence it becomes awkward to extract the analogous V_GS value.

Implementation of NMID Process on Test Device

The technique was implemented on the test device. Smooth curves were obtained. Flat curves of NMID to evaluate NMID max was challenging to extract the analogous threshold values. Figure 18 represents the NMID function output curve versus V_GS to extract V_TSAT for V_DS = 0.9 V.

The outcome of the result was as follows:

at

at.

5.3. Normalized Reciprocal H Function (NRH) Method

The NRH method can also be labelled as “Improved NMID Method”. Eliminating the ‘‘1’’ term and the factor ‘‘2’’ from NMID Equation (11), and considering that I_D ≠ 0 at V_GS = 0, yields a normalized version of the NRH function originally proposed in 2001 for extracting the threshold voltage of amorphous thin film MOSFETs, and later revised in 2010 to evaluate the sub-threshold slope of MOSFETs. Mathematically, the H function is represented as follows [33] [34] :

; (10)

where I_D0 is the drain current at V_GS = 0. Limit of the integral can be considered as 0 to V_GS in Equation (10). We propose that instead of using H(V_GS) function, its reciprocal NRH(V_GS) should be used to produce narrow maxima or minima:

(11)

A factor of 2 is added to the denominator in Equation (11) to allow a simple graphical explanation of its meaning. The numerator divided by 2 is the area of a triangle with a width of V_GS and a height of I_D − I_D0. Then, NRH is the ratio of this triangle’s area divided by the area under the plot (the integral). Figure 19 and Figure 20 illustrate the application of this NRH method to the test device for the extraction of V_TLIN and V_TSAT respectively.

Implementation of NRH Method on Test Device

The technique was implemented on the test device. Smooth curves were obtained. Flat curves of NRH to evaluate NRH max was challenging to extract the analogous threshold values.

The outcome of the result was as follows:

at

at.

5.4. Reciprocal H Function (RH) Method

In view of TCR, the differential value of I_D by itself expressively increases experimental noise, specifically in weak inversion, an analogous function for low gate bias. The plot of dRH/dV_GS versus V_GS exemplifies the above statement as it can be clearly seen in Figure 21 and Figure 22. The technique was proposed in 2010 based on the integration rather than differentiation to reduce unsolicited signal interference noise [33] [34] :

(12)

where RH is the reciprocal of function H predefined in NRH method; I_D0 is the drain current flow at V_GS = 0. Limits of the integral can be considered as 0 to V_GS. It is anticipated that the RH function could also be used to extract the threshold voltage. The V_TH can be extracted from the maximum negative gradient of the function RH i.e. V_GS = V_TH analogous to the minimum value of curve dRH/dV_GS.

Implementation of RH Method on Test Device

The technique was implemented on the test device. The method was highly affected by the investigational noise. Hence it was challenging to extract the threshold values. As seen in Figure 22 and Figure 23, distinct features like smoothening and filtration of the curve were considered to extract the correct output.

The outcome of the result was as follows:

at

at.

6. Self-Extraction Methods

These methods use the self-extracting techniques and circuits to extract the value of threshold voltage. Couple of methods under this category are briefly discussed below.

6.1. HSPICE Command Extraction Method

A substantially enhanced HSPICE feature that extracts MOSFET threshold voltage (V_TH) based on the constant-current definition universally adopted by fabrication labs to measure, specify, and monitor V_TH. Introduced in the 2009.09 release, HSPICE simulations compute constant-current V_TH the exact same way V_TH is measured in the fab [35] [36] .

For extracting V_TH, the “.OPTION IVTH” command is available. This .OPTION IVTH feature is supported for Levels 54 (BSIM4), 69 (PSP100), and 70 (BSIMSOI4) MOSFET models along with latest PTM nano-MOSFET models. It shows acceptable results. This command extracts V_TH using CCM and eliminates the use of I_DCRITICAL. LX142 model accessible in HSPICE, presents the output results as V_TH. Therefore, for short channel devices this process appears effectual in extracting V_TH and also shows compatibility with the existing transistor models.

The HSPICE Command “.OPTION IVTH” was implemented on the test device. LX142 model accessible in HSPICE, presents the output results as V_TH.

The outcome of the result was as follows:

at

at.

6.2. Automatic Threshold Voltage Extractor Circuit (ATEC) Method

This proposed ATEC method implements the most popular industrial extraction algorithm (LEM) of biasing a saturated MOSFET to the linear portion of its versus V_GS characteristics and extrapolating the tangential line to V_GS axis [37] [38] . The circuit accomplishes both the tasks automatically in continuous time irrespective of dimensions and technology of device under test. A simple feedback loop utilizing a Differential Difference Amplifier (DDA) achieves auto biasing, while another DDA computes the extrapolated value. The circuit is valid for both PMOS and NMOS devices and is able to forecast the value of V_TH using the proposed logic. Conceptual Schematic of ATEC is shown in Figure 24.

Few other similar ATEC designs with different implementation logics are also proposed to extract the V_TH.

Implementation of ATEC Method on Test Device

The technique was implemented on the test device. The bulk driven 10 nm nano- NMOS model was used to simulate the circuit. The test device is made to work in linear region. Hence the outcome will be the threshold voltage in linear region (V_TLIN). The transient analysis of the circuit gave the following results as shown in Figure 25.

for.

7. Deviation Based Extraction Methods

Under this grouping, the V_TH is extracted by determining either the deviation of the value or the difference between the measured values. Couple of methods using this logic are listed in this category and are briefly discussed below [39] .

7.1. Match-Point (MP) Method

Match-Point method was proposed in 1990 by B. El-Kareh and co-workers. This scheme subjectively evaluates V_TH at the value of V_GS at which the exponential subthreshold current semi-log extrapolation diverges by 5% from the measured I_D.

This MP method exaggerates the weak inversion region neglecting strong inversion. Figure 26 and Figure 27 present the application of this method to the linear region

and saturation region our test device producing an apparent V_TH value V_TLIN of 0.51 V and V_TSAT of 0.52 V respectively. Of course, diverse values of V_TH could be arbitrarily achieved by defining the deviation of the extrapolation at threshold at other values different from 5%. The shape of the semi-log curve may be swayed by the presence of parasitic resistance and other SCEs. This method is seldom used as it is more laborious and time consuming.

Implementation of MP Method on Test Device

The technique was implemented on the test device. Generally Match Point method is used to calculate threshold Values by plotting I_D versus V_GS curve with low biased drain terminal. Hence outcome is V_TLIN. The results are extracted by using the semilog plot. We propose to calculate V_TSAT by plotting versus V_GS and applying the same 5% deviation logic of Match point method. It was observed that V_TLIN value was lower than V_TSAT value which is generally unusual.

The outcome of the result was as follows:

at

at.

7.2. Vin-Vout Difference (VVD) Method

In this VVD method, a new interpretation of the threshold voltage is presented as [40] :

(13)

The method is implemented by performing the transient analysis on the testing device. In other words, it states that V_TH can be extracted by the voltage difference between the constant V_G and V_S at the normalized current in the I_D-V_S curves. As seen in Figure 28, the circuitry of VVD and the extraction method is straightforward and can be easily applicable in measurement apparatus [27] .

Implementation of VVD Method on Test Device

The technique was implemented on the test device. Figure 29 represents the transient

results of the VVD circuit. The circuit was compiled and simulated using SPICE. The circuit was analysed using predictive technology model (PTM) at 10-nm, 16-nm, 22-nm, 32-nm, and 45-nm technology node. The input gate voltage was set as 0.9 V. The Vdd was given as constant DC supply of 0.9 V. The multiple values of Load Capacitances (Cload) were used for the testing purpose, however, the V_TH extraction results had negligible effect of the variations in the value. Transient analyses were performed on the compiled circuit to extract the threshold voltage value.

The outcome of the result was as follows:

at and.

The transient results gave the V_out value marginally equal to V_in, slightly a bit millivolts lower than V_in. Hence, as per the above mentioned logic of the referred extraction method, the calculated V_TH is a very small value in millivolts which was not in accord with other extraction method outcomes. The extracted threshold voltage value also seems to be unrealistic. Hence we can accomplish that the VVD extraction method is considerably ineffective at nano-meter technology node.

8. Hybrid Extraction (HEM) Methods

Under this category, the HEM process uses multiple recognized schemes to extract V_TH and combines the advantage of each. One of the hybrid extraction methods is explained below [34] .

This Hybrid extraction method overwhelms the constraints of above mentioned extraction techniques and compute V_TH for all values of V_DS. It syndicates both methods namely CCM and LEM mentioned beforehand to appropriately extract the V_TH. Additionally, this method is also unaffected by the arbitrary value of I_DCITICAL. For valuation of V_TH using this method first the value of V_TH for low biased V_DS is attained using LEM (see Figure 30). Subsequently, I_DCRITICAL is determined using CCM as mentioned above. Further, for higher value of V_DS, V_TH is defined as the gate voltage at I_D for pre-calcu- lated I_DCRITICAL value. However, the extracted value of V_TH is not constant as the dependence of g_m on other process parameters is not modelled accurately.

Implementation of Hybrid Extraction Method on Test Device

The HEM technique was implemented on the test device. V_TLIN was calculated using LEM for I_D versus V_GS graph with low biased V_DS, and correspondingly the I_DCRITICAL was also evaluated. Furthermore, I_D versus V_GS graph is plotted with high biased V_DS. Implementing the CCM technique on the plot by using the pre-calculated I_DCRITICAL, we are able to calculate V_TSAT. Hence we are able to extract V_TLIN and V_TSAT using Hybrid extraction method as seen in Figure 30.

The outcome of the result was as follows:

at

at.

9. Compiled Simulation Results

All the predefined threshold voltage extraction methods were investigated and implemented at 10-nm Technology node and other sub 45-nm technology node. All the results are verified by extensive 2-D TCAD simulation and confirmed analytically. Various predictive technology models developed by the Nanoscale Integrations and Modelling (NIMO) Group at Arizona State University (ASU) were used to illustrate the characteristics of nano-MOSFETs. The models possess the competency to support short

channel effects, the gate leakage effects and various other second order effects to predict the realistic output. Table 1 presents a comparative result of largely applied threshold extraction methods for bulk driven nano-MOSFETs various sub 45-nm technology nodes. The V_TH was analysed using predictive technology model (PTM) for bulk driven nano-mosfet at 10-nm, 16-nm, 22-nm, 32-nm and 45-nm technology node.

The results are tabulated in Table 1. Accuracy can be enhanced by considering more number of measured points.

10. Application of V_TH Extraction Methods to Implement Noise Analysis

Noise analysis of the Resistive load Inverter were performed using various V_TH extraction method values. Resistive load inverter is one of the most fundamental circuits of MOS family. It characterizes the basic operation of all static gates. With Load resistor (R_L) in series with driver NMOS transistor, it has one input connected to the gate of NMOS and one output port connected to the drain terminal of the NMOS as shown in Figure 31. The Inverter Threshold Voltage V_TH (inverter) is the value where output voltage is equal to input voltage.

Noise margin is the limit of noise that a circuit can endure without compromising the operation of circuit. It assures that logic “1” with finite noise added to it, is still recognized as logic “1” and not logic “0” and vice versa. It is principally the difference between

signal and Noise value. Logically, the reference terms related Noise Margin analysis are described as below (Ref. Figure 32).

・ V_OH: (Voltage Output High Value). V_OH = Vdd because when the input voltage drops below V_TH of the inverter, no current flows. No current flow in turn means no voltage drop across the load resistor and V_OUT = V_dd = V_OH.

・ V_OL: (Voltage Output Low Value). If the input is driven to V_OL = V_dd, then the driver NMOS transistor is “ON” and since (V_gs − V_t) > V_ds, it is operating in linear mode. The V_OUT will be at V_OL and the V_IN will be at V_OH.

・ V_IH: (Voltage Input High Value). When V_IN = V_IH, the output is at V_OL and the NMOS is in the linear region.

・ V_IL: (Voltage Input Low Value). To determine noise margin we need V_IL which is one of two points where we have unity gain. When input low, output high and NMOS in saturation.

10.1. Introduction

Considering the output characteristics of a resistive load inverter; the threshold voltage of the NMOS (V_TH) plays a significant role in determining the shape of the voltage transfer characteristic (V_TC) of a resistive load inverter. The V_TH appears as a critical parameter in expressions for V_OL, V_IL, and V_IH. V_OH is determined primarily by the power

supply voltage V_dd. The adjustment of V_OL receives primarily attention than V_IL, V_IH. Larger V_TH results in smaller V_OL resulting in larger transition slope and higher voltage swing as it can be perceived through Figure 33.

10.2. Noise Margin Analysis of Inverter for Diverse Values of Driver NMOS Threshold (V_TH)

Ideally, when input voltage is logic “1”, the output voltage is expected to be at logic “0”. Hence, V_IH is V_dd, and V_OL is 0 V as shown in Figure 34. Alternatively, when input voltage is logic “0”, output voltage is supposed to be at logic “1”. Hence, V_IL is 0 V, and V_OH is V_dd. Using the values, the Noise Margins for an ideal inverter could be defined as follows:

・ NM_L (Noise Margin Low)

・ NM_H (Noise Margin High)

Practically the situation is not identical. It is observed that due to number of secondary effects like voltage droop, ground bounce, internal resistances, practices, etc.; V_OH is slightly less than V_dd i.e., whereas V_OL is slightly higher that V_ss i.e. as shown in Figure 33. Hence Noise margins for a practical circuit can be defined as follows:

・ NM_L (Noise Margin Low);

・ NM_H (Noise Margin High).

Hence, if input voltage (V_IN) lies somewhere between V_OL and V_IL, it would be detected as logic “0”, and would result in an output which is acceptable. Similarly, if input voltage (V_IN) lies between V_IH and V_OH, it would be detected as logic “1” and would result in an output which is acceptable.

10.3. Statistical Inference

Application of the extraction methods were implemented to calculate the Noise Immunity and Noise Margins for Resistive Load Inverter using 10-nm test device with Load Resistance R_L = 100 Ω and V_dd = 1 V. Referring to Table 2, we can infer number of facts and properties that can be extracted from noise margin analysis regarding various threshold extraction methods.

・ We observe that with the increase in the Threshold voltage extraction value, the NM_H decreases and NM_L increases. For an Ideal Inverter, Noise Margins should be equal. Using QEM method for V_TH extraction, we obtain the most optimistic results (NM_H ≈ NM_L) in this regards. (Ref. Figure 35 and Figure 36).

・ Using “.OPTION IVTH” command accessible in SPICE extraction method for V_TH extraction, we obtain the maximum output voltage swing i.e. V_OH − V_OL for resistive load NMOS inverter (Ref. Figure 37).

・ In the well-designed inverter, the Threshold value of the circuit (V_in = V_out) is nearly equal to V_dd/2. We obtain the flawless results in this regards using CCM extraction method (Ref. Figure 38).

・ The slope of the output curve within the transition region describes the propagation delay properties of the circuit. The variation in the V_TH had a negligible effect on the slope of the curve resulting in nearly persistent switching characteristics for most of the extraction methods.

11. Conclusion

We presented, reviewed and critically compared several extraction methods currently used to determine the threshold voltage of bulk driven MOSFETs at 10-nm technology node and other various sub 45-nm technology nodes for precise evaluation of the respective method. The relative performance of all the methods was illustrated and compared under similar conditions by applying them to the test devices: bulk driven nano-MOSFETs with 10-nm technology node along with other various sub 45-nm technology nodes. We can perceive that the extracted threshold voltage largely depends on the method used for extraction specifically at nano-scale. The CCM has an ambiguous definition on the critical drain current (I_D0) contingent on technology being used. The LEM, QEM and TM outcomes are affected by extrinsic resistance effects, mobility degradation, Short Channel Effects and other second order present effects. SD, TD, GM, RH and TCRM are also widely affected by noise and are also not based on ideal threshold voltage definition condition. The MP is seldom used as 5% deviation value gives an ambiguous definition of threshold. The VVD extraction method is considerably ineffective at nano-meter technology node. In NMID and NRH, the correct calculation of maxima in wide ranges makes the extraction task much more difficult. We can also infer number of facts and properties from noise margin analysis performed using various threshold extraction methods. QEM provides the most optimistic balanced noise margin results. The maximum output voltage swing was observed using SPICE extraction method. CCM delivers the most appropriate results in calculating Threshold value of the circuit. The above listed features and properties of various extraction methods can be helpful in merging the threshold voltage compact models at nano-level technology nodes.

Cite this paper

Swami, Y. and Rai, S. (2016) Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node. Circuits and Systems, 7, 4248- 4279. http://dx.doi.org/10.4236/cs.2016.713349

References