be different in order to produce two different pseudorandom binary sequences.

Certain easy to use control settings are employed in order to insert a stuck-at-0 or stuck-at-1 fault at a location selected by the user. Bits can be targeted easily with permanent injection by means of the StuckAtBit and StuckAtValue in the injection block. StuckatBit is the location of the permanent fault and StuckAtValue is the logic value of the stuck-at fault. The flow for data that will have permanent injection of a fault is shown in Figure 4.

The easiest way to accomplish control of the system is with a simple generic port map in VHDL that is used for the fault injection logic block in the system. A control code that is 4 bits wide is used in the highest level block, the control logic module, in order to let the user to change the rates of fault injection.

2.2. Fault Injection Logic Block and One-Hot Encoded Shift Register

The Fault Injection Logic block is the heart of the injection system that bears the work of incorporating data from the two LFSR’s and also the One-Hot Encoded shift register. The block monitors the control inputs to the circuit to evaluate whether it needs to perform transient or permanent fault injection in the data that is sent to it. The control code which initializes permanent fault injection is “1111”. If “1111” is sent to the injection system, the fault injection logic inserts a stuck-at fault at the location that is specified by the user (StuckAtBit) to the value (StuckAtValue) that is specified by the user. Otherwise, injection is determined to be of the transient nature. It must be made clear that the system operates differently when this “1111” is passed to it in the form of a control code. That code is the only one that uses StuckAtBit and StuckAtValue.

Other control codes are for transient injection and range from “0001” ® 50% injection to “1110” ® < 0.01% injection. A control code of “0000” is 0% fault

injection while a control code of “1111” is 100% fault injection. The control code is used to control the point in time at which the fault is injected. By incrementing this control code by “1” for each code, fault injection is dropped by 1/2 from the previous rate.

In order to determine the bit on which a fault will be inserted during transient fault injection, a one-hot encoded shift register is used. Every clock cycle, a logic “1” is shifted through a data word that is the length of the data word sent to the injection system. The purpose of the “1” is to determine on which bit the fault will be injected. When the control logic has seen that a fault is to be injected, it views the data output word of the one-hot encoded shift register. On the bit which is a “1” the control logic flips the bit in the data word.

The Fault Injection Logic block constantly monitors the output of both of the LFSR’s, determining whether a fault is to be injected or not. It also determines on which bit a fault will occur if more than one bit is sent to the injection system. The Fault Injection Logic block sends to the Control block the same data word that was passed into the system or a faulty data word based on whether a fault has been calculated to occur.

2.3. Control Logic for Fault Insertion

The Control logic allows the user to change rates of fault insertion during operation. It does this by operating in parallel 15 different Fault Injection Logic blocks. The output of a certain Fault Injection Logic block is directed to the output of the injection system by multiplexing the 16 total different signals to the output of the injection block based on the 4-bit wide control code, as discussed in the previous section. If the fault injection system is not activated, the data that is sent into the system is directed out. But if the system is active, then a fault is inserted on the data word coming into the system and directed to the data out word.

2.4. Component Instantiation

In behavioral or structural design approach within VHDL, the component instantiation is the same. With predominately behavioral design approaches being used in system design especially in describing complex state machines, it is not possible to predict the structure of the circuit generated by the synthesis tool. Therefore, a generic instantiation block as shown in Figure 5 is employed in the proposed fault injection technique.

In Figure 5 DataLength is the length of the primary input or internal signal on which a fault will be injected. It is just a positive integer that is needed in order for the fault injection system to operate, and should be the same as the number of bits that are contained in a signal or primary input that is being fed to the system for fault injection. For example, for a single bit that is sent to the system for injection, DataLength is 1. For a 4-bit wide word whereby faults will be inserted, DataLength is 4. DataIn is the signal or primary input from the VHDL block that is calling this instantiation for which a fault will be inserted. DataOut corresponds to the output of the block that may contain a fault. Faults injected by the system are placed on the data coming from DataIn and seen on DataOut. DataIn and DataOut must be of the same width and must be DataLength bits long. Ctrl codes are 4 bits wide and range from “0000” to “1111”. “0000” corresponds to no fault injection and “1111” corresponds to permanent fault injection. Clk is a system clock that is needed to be turned on for both transient and permanent fault injection. The Reset signal resets all flip flops in the system and must be enabled for at least one clock cycle at the beginning of a simulation followed by the load signal one to two clock cycles later. Match is simply an output signal denoting a fault has occurred and enable allows the system to inject faults onto incoming data. StuckAtBit and StuckAtValue are only useful when permanent fault injection in the system with a control code of “1111”. StuckAtBit is the bit on which a permanent fault is injected, and StuckAtValue is the logic value (0 or 1) that the bit selected by StuckAtBit is set to.

2.5. Injection Block Placement

The proposed fault injection system is able to inject faults into both combinational and sequential parts of VHDL descriptions and into behavioral or structural VHDL coding. With predominately behavioral design

approaches being used in system design especially in describing complex state machines, it is not possible to predict the structure of the circuit generated by the synthesis tool. Since in most cases only the behavioral description of a sequential circuit is available, the ability to inject faults in the VHDL description of the sequential circuit is imperative in order to have the capability to assess the controllability and observability of the eventual circuit resulting from the VHDL description.

The fault injection block is not meant to be able to inject faults on every signal within a VHDL description, but to reach as many low-level VHDL blocks containing primary inputs and outputs, internal signals therein as possible.

3. Fault Injection System in Practice

The application of the proposed fault injection system is illustrated through several examples. The VHDL coding and compilation in the following examples utilized the Xilinx Foundation 5.1.03i, and the simulation was performed in ModelSim XE II 5.6a. In order to write VHDL in the in the Xilinx Foundation, a specific FPGA had to be chosen; the FPGA XC2V500-4FG456C was selected for this purpose.

3.1. Transient Fault Injection in Online Testable Systems

To illustrate the use of fault injection in an on-line testable circuit, the fault injection block must be inserted into a VHDL block that is meant to be self-checking. A self-checking circuit can determine whether a fault has propagated to an output data word or not. Thus, a coding system must be employed to accomplish the self-checking aspect of the circuit and a checker that accepts coded data. For this example, a 2-out-of-4 code is used for the method of data encoding. In other words, for every 4-bit word of data that is going through the system, 2 bits in each word are 1s and the other two are 0s. The fault injection block is placed as shown in Figure 6. Subsequently, data is fed from the fault injection block to the 2-out-of-4 code checker which is shown in Figure 7. When Z1 Z2 = 01 or 10, the circuit under test is fault-free, where as Z1 Z2 = 00 or 11 indicates the presence of a fault.

The 2-out-of-4 Code Generator circuit is assumed to have 3 inputs (I1, I2, I3) and a 2-out-of-4 code as the output (O1, O2, O3, O4). The sum of products notation for the example circuit is:

O1 = ∑ (0, 3, 5, 6)

O2 = ∑ (1, 3, 4, 6)

O3 = ∑ (2, 4, 5, 7)

O4 = ∑ (0, 1, 2, 7)

The VHDL code for the circuit is shown below:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;

use work.lfsr_pkg.all;

entity test1 is

        Port (DataOut: out std_logic_vector(3 downto 0);

          clk,reset,load,faultenable : in std_logic;

          ctrl : in std_logic_vector(3 downto 0);

          CircuitIn : out std_logic_vector(2 downto 0);

          match : out std_logic;

          fault : out std_logic;

          Z1,Z2 : out std_logic);

end test1;

architecture Behavioral of test1 is

        signal i : std_logic_vector(2 downto 0);

        signal DataIn : std_logic_vector(3 downto 0);

        signal subdata : std_logic_vector(3 downto 0);

begin

-- The LFSR serves the function of feeding inputs to the

-- circuit so it will not have to be done manually in the

-- simulator

LFSR1: LFSR_GENERIC

                   generic map (Width => 3)

                   port map  (clock => clk                   

                                   reset => reset                

                                    load => load                                    

                                    seed => “101”                                  

                                    parallel out => i);

        CircuitIn <= i;

-- DataIn(3) = O1, DataIn(2) = O2, DataIn(1) = O3, DataIn(0) = O4

        DataIn(3) <= (NOT i(0) AND (i(1) XNOR i(2))) OR (i(0) AND (i(1) XOR i(2)));

        DataIn(2) <= i(0) XOR i(2);

        DataIn(1) <= (NOT i(2) AND (i(0) XOR i(1))) OR (i(0) AND i(2));

        DataIn(0) <= (NOT i(0) AND NOT i(1)) OR (i(1) AND (i(0) XNOR i(2)));

-- Fault insertion block instantiation

inserter: faultblock

generic map(DataLength => 4,

          StuckAtBit => 0)

-- The value for StuckAtBit does not matter in this case

-- because a transient fault is going to be injected, thus

-- letting the injection system handle when and where the

-- fault occurs

-- The 4 indicates the length of the data word for which a

-- fault shall be injected

port map (DataIn => DataIn,

                          DataOut => subdata,

                          StuckAtValue => ‘0’,

-- StuckAtValue does not matter in this case because

-- once again, the system in transient injection is handling

-- the location and what the fault will be

                          ctrl => ctrl,

-- Set ctrl anywhere between “0001” and “1110” for

-- transient fault injection

-- If ctrl is used as an input to the circuit, it can be changed

-- during operation or it can be set manually within the

-- injection block (ctrl => “0001”)

                   clk => clk

                           reset => reset

                   load => load

                   enable => faultenable);

        DataOut <= subdata;

-- 2 out of 4 checker Z1 <= (subdata(0) OR subdata(1)) AND (subdata(2) OR subdata(3));

Z2 <= (subdata(0) AND subdata(1)) OR (subdata(2) AND subdata(3));

end Behavioral;

Figure 8 shows the simulation results of the 2-out-of-4 encoder operating at 100 MHz without fault injection occurring. The circuit inputs are generated by a 3-bit linear feedback shift register (LFSR) and are fed directly to the circuitry described above in O1, O2, O3, & O4. The resulting 2-out-of-4 code words are verified by the code checker as shown in Z1 and Z2.

Figure 9 shows simulation results with the fault inject-

tion block turned on; the control code is set at 0001 i.e. the rate of fault appearance is 50%. As can be seen in the diagram for certain input combinations Z1 and Z2 are either 00 or 11. After a few clock cycles, fault insertion stops briefly to allow normal operation. This makes Z1 and Z2 to become 01 or 10. Towards the end of the diagram Z1 and Z2 become 11 and then 00 indicating the presence of a fault in the data word. This can be verified by observing the “dataout” word which is producing a non-code word.

3.2. Permanent Fault Injection in an Off-Line Testing Environment

To further illustrate the functionality of the system, an example showing permanent injection of a single stuck-at fault is provided. The test pattern generator in this case is a 3-bit LFSR. The control code is set at 1111.

There is no on-line checker in this case, the outputs need to be observed to ascertain the effect of the stuckat-1 fault being introduced on the 0-bit in the data word. The fault injection block is shown in Figure 10.

Figure 11 shows the simulation results in the absence of a fault. The expected outputs can be observed on the Datout line. From the simulation results in Figure 12, it can be concluded that the circuit is operating with a stuck-at-1 fault on bit 0 in the data word, as indicated in the specifications of the injection block in Figure 10. It should be noted that that the fault injection block of Figure 10 can insert either a transient or a permanent fault simply by changing the control code even during normal operation. However, the location of the permanent cannot be changed during operation.

4. Transient and Permanent Fault Injection in a Sequential Circuit

The fault insertion technique proposed in [5] considered combinational logic circuits only With predominately behavioral design approaches currently being used in system design especially in describing complex state

machines, it is not possible to predict the structure of the circuit generated by the synthesis tool. Since in most cases only the behavioral description of a sequential circuit is available, the ability to inject faults in the VHDL description of the sequential circuit is imperative in order to have the capability to assess the controllability and observability of the eventual circuit resulting from the VHDL description. The fault injection block is not meant to be able to inject faults on every signal within a VHDL description, but to reach as many low-level VHDL blocks containing primary inputs and outputs, internal signals therein as possible

If Z1, Z2 = “01” or “10”

® Circuit is behaving normally

If Z1, Z2 = “00” or “11”

® Circuit is operating with a fault

For sequential circuits, the states must be set outside a process statement in order for the injection system to

operate. The process statement may however contain a signal representing the state of the machine. The signal that identifies the new state of the machine is used in the DataIn assignment in the injection block. The new state of the machine is on DataOut. The new state may or may not contain an injected fault. The component instantiation for the system cannot be implemented within a process statement. An example sequential circuit that includes a fault injection block is shown in Figure 13. Figure 14 shows the simulation results of the sequential circuit described in Figure 13 operating under normal conditions. Figure 15 shows the circuit operation with a 50% fault injection rate. As can be seen in the diagram the counter is going through erroneous state transitions. Figure 16 shows the circuit operation with permanent fault injection for a stuck-at-1 on bit 0 of the counter registers. It should be clear from the diagram that the circuit states are erroneous.

5. Conclusion

A fault injection technique that enables designers the access to a VHDL package to insert a fault on any signal within the block of a VHDL code, has been presented. It allows the injection of transient faults randomly across a data word, and allows the insertion of a permanent fault at any chosen point in a data word. A number of examples are provided to illustrate the use of the proposed fault injection system in onand off-line testing environments for both combinational and sequential circuits. A major advantage of the proposed approach is that the fault insertion process is significantly simpler than other currently available approaches. Since the fault insertion block is included in a package, much like a library in other forms of programming, only a simple call at the beginning of the VHDL description and a component instantiation is needed to activate the insertion mechanism.

6. Acknowledgements

This work was supported in part by the National Science

Foundation, USA under Grant 0925080.

REFERENCES