ared to 50% of Empire model predictions of the test data are within 10% of the measured values of time. Furthermore, 80% of the ANN predictions of the test data are within 20% of the measured values of the time while 90% of Empire model predictions of the test data are within 20% of the measured values of time. It is clear that the Empire predictions of time are slightly better than the ANN model prediction which corroborate with the results from the performance criteria presented earlier.

Table 4 shows the prediction and accuracy of the ANN model and the Empire model based on the test data set as compared to the measured values of area. It is observed that 45% of ANN model predictions are within

Table 3. Prediction and accuracy of time of test data.

Table 4. Prediction and accuracy of area of test data.

10% or less of the measured values of area compared to 25% of Empire model predictions of the test data are within 10% of the measured values of area. Also, 70% of the ANN predictions of the test data are within 20% of the measured values of the area while only 45% of Empire model predictions of the test data are within 20% of the measured values of area. It is clear that the ANN predictions of area are better than the Empire model predictions. This corroborates the results of the performance criteria presented earlier in Table 1.

Parametric Study

To further compare the performance of the Empire model and the ANN model in predicting the time and the area, we varied the input parameters (width, ports, and depth) and computed the resulting outputs for 6 designs. Figures 4 and 5 depict comparative plots showing the predictions of time and area respectively for varied combinations of parameters.

From Figures 4(c) and (d), it is clear ANN model predictions are fairly accurate when the number of ports is varied with a fixed depth and width. Figure 3(b) shows that the ANN model when the width is increased with the depth and ports parameters fixed has underestimated the time specially with wider designs. Similarly, when the depth is varied while keeping the width and ports fixed (Figures 4(e) and (f)), the ANN predications were relatively above and below the experimental values in few cases.

In the instances selected for area comparison (Figure 6), both models performed relatively well and the predicted areas were close to the experimental values obtained from detailed simulation. However, overall and as the statistical results of Table 2 indicate, the ANN model has outperformed the Empire in area prediction.

From the aforementioned analysis of results and validation of the ANN model, it is evident that the proposed ANN model can be used to provide designers with representative estimates of the time and area of a perceived register file design before committing to silicon. The time and the area estimates for all the register file designs used in this study with 130 nm technology and a supply voltage of 1.2 V are shown in Figures 6 and 7 respectively.

5. Conclusions

The continued trend in microprocessors design towards wider instruction issue and large instruction windows implies register files will have to be designed with large sizes and a large number of read/write ports. Consequently, this will lead to additional power consumption by these large-sized files and a noticeable impact on cy-

Figure 4. Comparison of time for selected register files.

Figure 5. Comparison of area for selected register files.

cle time. Therefore, models and tools that allow designers to predict the area and the timing of a given design prior to committing to silicon are of great benefit to microprocessors designers. Evaluating architectural tradeoffs early in the design cycle provides designers with insight into the performance of a design, and shortens the time-to-market window.

In this paper, we proposed a novel neural network model for estimating the timing and size or area for register file designs. The model is simple and efficient and can be used to provide estimates that are close to those expected when detailed and time consuming simulation is performed. The model is validated by comparing its results to those produced by low level simulation, as well as by comparing it to the recently reported Empire model [11].

Figure 6. ANN model for time for all ports.

Figure 7. ANN model for area for all ports.

6. Acknowledgements

The authors would like to thank Dr. Praveen Raghavan of IMEC in Belgium for providing the register file designs data for the 130 nm technology node.


  1. R. Preston, et al., “Design of an 8-Wide Superscalar RISC Microprocessor with Simultaneous Multithreading,” SolidState Circuits Conference, Vol. 1, 7 February 2002, pp. 334-472.
  2. N. S. Kim and T. Mudge, “The Microarchitecture of a Low Power Register File,” Proceedings of the 2003 International Symposium on Low Power Electronics and Design, Seoul, 25-27 August 2003, pp. 384-389.
  3. R. Balasubramonian, S. Dwarkadas and D. H. Albonesi, “Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” Proceedings of the 34th annual ACM/IEEE International Symposium on Microarchitecture, Austin, 1-5 December 2001, pp. 237-248.
  4. Y. Tanaka and H. Ando, “Reducing Register File Size through Instruction Pre-Execution Enhanced by Value Prediction,” Proceedings of the 2009 IEEE International Conference on Computer Design, Nagoya, 4-7 October 2009, pp. 238-245. doi:10.1109/ICCD.2009.5413149
  5. S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi and J. D. Owens, “Register Organization for Media Processing,” Proceedings of the 6th International Symposium on High Performance Computer Architecture, Stanford, January 2000, pp. 375-386.
  6. J. Tseng and K. Asanovic, “Energy Efficient Register Access,” Proceedings of the 13th Symposium on Integrated Circuits and Systems Design, Cambridge, 2000, pp. 377-382.
  7. K. M. B Ahin, P. Patra and F. N. Najm, “ESTIMA: An Architectural-Level Power Estimator for Multi-Ported Pipelined Register Files,” Proceedings of 2003 International Symposium on Low Power Electronics and Design, Hillsboro, 25-27 August 2003, pp. 294-297.
  8. N. Kahraman and T. Yildirim, “Technology Independent Circuit Sizing for Standard Cell Based Design Using Neural Networks,” Digital Signal Processing, Vol. 19, No. 4, 2009, pp. 708-714. doi:10.1016/j.dsp.2008.11.009
  9. F. Djeffal, M. Chahdi, A. Benhaya and M. L. Hafiane, “An Approach Based on Neural Computation to Simulate the Nanoscale CMOS Circuits: Application to the Simulation of CMOS Inverter,” Solid-State Electronics, Vol. 51, No. 1, 2007, pp. 48-56. doi:10.1016/j.sse.2006.12.004
  10. P. Kalpana and K. Gunavathi, “Wavelet Based Fault Detection in Analog VLSI Circuits Using Neural Networks,” Applied Soft Computing, Vol. 8, No. 4, 2008, pp. 1592- 1598. doi:10.1016/j.asoc.2007.10.023
  11. A. Suissa, O. Romain, J. Denoulet, K. Hachicha and P. Garda, “Empirical Method Based on Neural Networks for Analog Power Modeling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, 2010, pp. 839-844. doi:10.1109/TCAD.2010.2043759
  12. P. Raghavan, A. Lambrechts and M. Jayapala, F. Catthoor and D. Verkest, “EMPIRE: Empirical Power/Area/ Timing Models for Register Files,” Microprocessors and Microsystems, Vol. 33, 2009, pp. 295-300. doi:10.1016/j.micpro.2009.02.009
  13. S. Haykin, “Neural Networks: A Comprehensive Foundation,” 2nd Edition, Prentice-Hall, Upper Saddle River, 1999.
  14. J. A. Abdalla and R. A. Hawileh, “Modeling and Simulation of Low-Cycle Fatigue Life of Steel Reinforcing Bars Using Artificial Neural Network,” Journal of the Franklin Institute, Vol. 348, No. 7, 2011, pp. 1393-1403. doi:10.1016/j.jfranklin.2010.04.005

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