Nowadays, transistor technology is going toward the fully depleted architecture; the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.
As the size of the transistor is downscaled, the decrease of the power consumption, the decrease of the leakage current, and the achievement of high performance should be taken into account. In bulk transistors, the two electrical terminals, source and drain, are built on doped silicon and the flow of electrons between them is controlled by the gate. As the transistor shrinks, the channel is reduced, the control of gate exercised over the channel region is reduced too, thus lowering the transistor performance [
In an ideal transistor, the channel potential is only controlled by gate voltage ( V g ) through gate capacitance. On the other hand, the channel potential, in a real transistor, is also subjected to the influence of drain voltage through drain capacitance, which is between the drain and the channel. When the gate length is large, the drain capacitance is much smaller than the gate capacitance and the drain voltage does not interfere with V ′ g s role as the sole controlling voltage. When the channel becomes short, the distance between source and drain gets smaller, and the drain capacitance becomes larger [
Two facts drastically reduce device performance: leakage is one of those, and variability is the other [
crystallographic orientation that leads to different work functions at the interface between the metal and the high-K material, that will cause a variation of the local threshold voltage in the gate area. The line edge roughness is a result from the variations in lithography and etching in fabrication process which causes a variation in the channel width and gate length.
The topics of this paper are outlined as follow:
・ Alternative Transistors: the current design solutions used to reduce transistor’s geometry and enhance the performance: UTBB FD-SOI and Tri-Gate FinFET.
・ Reliability Test for UTBB FD-SOI AND TRI-GATE: applying Hot Carrier Injection (HCI) and the breakdown of the gate oxide TDDB (Time Dependent Dielectric Breakdown).
・ Comparison Between 28-nm UTBB FD-SOI and 22-nm TRI-GATE FINFET: compares the physical and electrical characteristics of both transistors and determines the appropriate one to select for analog or digital applications.
・ Conclusion.
・ Future Work.
Minimizing the leakage current and improving the performance in bulk silicon transistor have been more complex when the node of the transistor arrived to 28 nm. In technology of about 28 nm and below, a new solution was introduced to reduce the complexity and to get the advantage of reducing transistor’s geometry: UTBB FD-SOI and Tri-Gate FinFET. Both transistors share CMOS technology with a fully depleted transistor architecture but make the transistor a better switch.
A 28-nm Fully Depleted Silicon on Insulator (FD-SOI) which was built without changing the fundamental geometry of the transistor lies on adding a thin insulator layer of buried oxide positioned under the channel as shown in
On the same technology node, the UTBB FD-SOI has smaller channel effective length 24 nm (PB0: poly-bias 0) compared to that of the bulk’s one 28 nm. Smaller channel length means shorter path flow for electrons. That reduces the time needed for the electrons’ flow from the source to the drain, leading to a fast transistor [
The buried oxide insulator layer confines the electron when flowing from the source to the drain as shown in
The very thin silicon layer enables the silicon under the transistor gate to be fully depleted of charges; therefore, it eliminates the random dopants fluctuation; as shown in
allows for lower drain/source capacitances and leakage currents in addition to the benefit of total latch-up immunity. Also, the reduction of the gate length decreases the gate capacitance and it has a raised source/drain epitaxy to reduce the access resistance. The saturation drain current, ID, as in Equation (1):
I D = 1 2 n μ C o x W L ( V G S − V T H ) 2 (1)
where μ : effective mobility, W: device width, L: channel length V G S : gate to source voltage, VTH: threshold voltage.
For the bulk transistor, n is as in Equation (2):
n = 1 + ε s i C o x X d max ≅ 1.4 to 1.6 (2)
For UTBB FD-SOI, n is as in Equation (3):
n = 1 + ε s i t s i C o x b C o x ( ε s i t s i + C o x b ) ≅ 1.05 to 1.1 (3)
where X d max : maximum depletion width, C o x : gate oxide capacitance, C o x b : buried oxide capacitance, t s i : silicon thickness.
Based on the above equations of n, it is clear that the current in UTBB FD-SOI will be higher than that of the bulk transistor by a factor of ×(1.3 − 1.4).
The Sub-threshold slope (SS) indicates how effectively the flow of drain current of a device can be stopped when Vgs is decreased below Vth. When Id − Vg curve of a device is steeper, sub-threshold slope will improve. It is characterized by steep sub-threshold slope that exhibits a faster transition between off (low current) and on states (high current). The sub-threshold slope factor depends on the capacitance of the CMOS technology as in Equation (4), which is degraded due to the insulated layer. The thickness of the insulated layer also plays a role on the capacitance value: as the thickness of insulated layer is increased, consequently capacitance decreases. Therefore, the sub-threshold slope will be decreased [
S t = K T q . ( 1 + C d C i ) (4)
where K T q is the thermal voltage, Cd is the depletion capacitance, and Ci is the gate oxide capacitance.
In the weak inversion regime, there is a potential barrier between the source region and the channel region. The height of this barrier is a result of the balance between drift and diffusion current between those two regions. The barrier height for channel carriers should be ideally controlled by the gate voltage to maximize trans-conductance. The DIBL (Drain Induced Barrier Lowering) [
The bulk DIBL is as in Equation (5):
DIBL = 0.8 ε s i ε o x ( 1 + X j 2 L e l 2 ) ⋅ T o x L e l ⋅ T d e p L e l ⋅ V D S (5)
where ε s i : silicon permittivity, ε o x : gate oxide permittivity, X j : junction depth, L e l : electrical channel length, T o x : gate oxide thickness, T d e p : depletion width in bulk transistor, V D S : Drain Source voltage.
The DIBL of UTBB FD-SOI is in Equation (6):
DIBL FDSOI = 0.8 ε s i ε o x ( 1 + T s i 2 L e l 2 ) ⋅ T o x L e l ⋅ T s i L e l ⋅ V D S (6)
where Tsi is the channel thickness.
By comparing Equation (5) and Equation (6), the UTBB FD-SOI has better DIBL than that of the bulk transistor because UTBB FD-SOI takes into consideration the ultra-thin channel, Tsi.
To improve the transistor performance, a voltage can be applied to the substrate. This method is called Body Biasing which facilitates the creation of the
channel between the source and the drain resulting a faster switching. Because of the ultra-thin layer in FD-SOI, the biasing creates a buried gate below the channel making the transistor act as a double vertical gate transistor. Scaling down the silicon thickness under the gate of a FD-SOI transistor below 5 nm [
This Ultra-thin body and BOX (UTBB) FD-SOI transistor architecture (7 nm silicon thickness and 25 nm BOX thickness) has a stronger body effect than bulk transistors and therefore enables effective threshold voltage (Vth) management through body biasing. The BOX thickness (25 nm) is a compromise between an increased parasitic source/drain to substrate capacitance and enhanced body effect. While in bulk technology, the ability of doing body biasing is limited due to the parasitic current leakage, the buried gate in UTBB FD-SOI prevents any leakage in the substrate. Thus, it allows much more voltage on the body leading to a significant boost performance. The range of back-gate biasing in UTBB FD-SOI is quite wider by a factor of 10 (i.e. −3 V < VBB < 3 V) compared to the bulk technology (−300 mV < VBB < 300 mV). And the slope of threshold voltage is 85 mV/V vs. 25 mV/V as shown in
The characteristics of UTBB FD-SOI vertical double transistor allow the creation of new concept in processor design. Different voltage can be applied independently at the top and at the buried gate [
characteristics of the transistor. By choosing the optimum voltages at the top gate and the buried one, the transistor characteristics can transform from high performance to low power transistor.
Since the leakage current strongly depends on the threshold voltage Vth, different Vth transistors can be optimized for speed and low power as shown in
the leakage current. That leads to a compromise between speed and power that the designer should balance.
Body bias can be used to vary the maximum frequency: while the FBB can be applied to increase the frequency, the RBB can be applied to decrease it. The dynamic body bias combined with a different voltage frequency scaling (DVFS) can provide the best performance power tradeoffs.
The lower leakage current makes the transistor less sensitive to the temperature;
The 28-nm UTBB FD-SOI offers two types of transistors to optimize leakage and performance: RVT (conventional well) and LVT (flip well) as seen in
In a conventional planar FET transistor, the current flowing through the channel is closely related to the width (W) of the device, divided by the length (effective L). As the industry scales to smaller nodes, it is ideal to decrease effective L, which improves the drive strength of the transistor. However, shorter transistors have less control over the channel and exponentially higher sub-threshold leakage. To control leakage, the channel is heavily doped, which makes everything more susceptible to variability. A 3D Tri-Gate transistor looks a lot like the planar transistor but with one fundamental change. Instead of having a planar inversion layer (where electrical current actually flows), Intel’s 3D Tri-Gate transistor creates a three-sided silicon fin that the gate wraps around, creating an inversion layer with a much larger surface area as shown in
The gate exerts more control over the flow of current through the transistor; it surrounds the channel on all three sides and has much better control so that all the charge below the transistor is removed (fully depleted) and there is no depletion capacitance, so it is tightly controlled. This reduces dopants variability because no―or lightly―doping is needed to control the channel. The “fully depleted” characteristics of Tri-Gate transistors provide a steeper sub-threshold slope that reduces leakage current (from 0 V to 0.4 V). The DIBL is given as in Equation (7) which is the lowest compared to bulk and UTBB FD-SOI transistors.
DIBL TRI-Gate = 0.8 ε s i ε o x ( 1 + T s i 2 4 L e l 2 ) ⋅ T o x L e l ⋅ T s i 2 L e l ⋅ V D S (7)
The steeper sub-threshold slope can also be used to target a lower threshold voltage, allowing the transistors to operate at lower voltage to reduce power and/or improve switching speed as shown in
The 22-nm Tri-Gate transistors are 18% and 37% faster at 1 V and 0.7 V respectively than Intel’s 32 nm transistors [
The Tri-Gate FinFET transistors are fully depleted so the carriers flow in
threshold and sub-threshold voltage in different places compared to where they flow in high gate bias condition. As seen in
dle at a low bias, and it passes at the surface at a high bias. Intel chooses the trapezoidal shape of the fin while in terms of performance the rectangular fin shape is optimum more than trapezoidal by about 15% [
The 3D nature of Tri-Gate FinFET transistor introduces a new number of parasitic capacitances to be considered. For example, between the gate and the source there will be two sided capacitors other than the top and the bottom capacitors as shown in
increases the parasitic resistance (from each fin) and adds interconnect capacitances between fins [
This paper provides an overview of the challenges faced by conventional CMOS scaling. It explains fully depleted devices, such as planar UTBB FD-SOI and Tri-Gate FinFET, as the alternative solutions of bulk transistors at 28-nm and beyond, shedding the light on their designs and performance.
A detailed comparison between 28-nm UTBB FD-SOI and 22 nm Tri-Gate FinFET transistors to be elaborated in later work will make a solid comparison
between them and will explain each technology features like: physical characteristics, electrical characteristics, and their reliability test.
Mohsen, A., Harb, A., Deltimple, N. and Serhane, A. (2017) 28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide―Part I. Circuits and Systems, 8, 93-110. https://doi.org/10.4236/cs.2017.84006