Threshold voltage (V TH ) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V TH value of the device is extracted and evaluated by several estimation techniques. However , these assessed values of VTH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent VTH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.
Incessant abridging of IC technology, together with precision of VTH control techniques and reduction in SCE, is asserting the VTH to very low values. For proper operation of MOSFET, we need to evaluate exact threshold voltage (VTH). Perfectly appraised VTH is required to provide proper gate control over device channel conduction (see
The threshold voltage parameter is largely extracted directly from the transfer characteristics of the device. There is no critical point in the ID-VGS curve that can be recognized as threshold point due to sub-threshold leakage current. This creates vagueness in VTH estimation. The weak inversion region shows exponential deviations while strong inversion shows linear/quadratic deviations. However, the VTH is identified amid weak and strong inversion transition region [
In consideration to the above, this paper presents the study and analysis of numerous VTH extraction methods at various sub 45-nm technology node. The outcomes of the analysis are implemented on a simple resistive load inverter for computing noise margins to infer the performance of various threshold voltage extraction methods at sub 45-nm technology node.
Rest of the paper is organized as follows. Section 2 categorizes several threshold voltage extraction methods on the basis of their assessment methodology. Section 3 to Section 8 discuss and evaluate the various mentioned threshold voltage extraction methods at 10-nm technology node and other sub 45-nm technology nodes. Further, Section 9 presents the tabulated compiled simulation results, comparison and discussion for various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented in Section 10. Finally, concluding remarks
are conferred in Section 11.
Ideally, VTH of a device is the critical gate voltage below which the drain to source current (ID) is zero, But practically, sub-threshold leakage current exists for VGS below VTH. As the drain current doesn’t drop abruptly to zero and hence, it becomes challenging to precisely determine the critical point at which switching of ID takes place. Due to this reason, several procedures presented in literature use diverse descriptions to extract the VTH of the MOSFET but still has a scope for improvement to correctly evaluate VTH [
For simplicity, the threshold extraction methods have been categorized into six main groups on the basis of their assessment methodology as:
1) ID based extraction methods;
2) Derivative of ID based extraction methods;
3) Integral of ID based extraction methods;
4) Self-extraction methods;
5) Deviation based extraction methods;
6) Hybrid extraction methods.
It is considered that the threshold voltage changes with the change in the operating region of the MOSFET specifically in linear/ triode region and saturation region. Distinctive efforts are made to accurately calculate the VTH in both the operating regions [
These methods use the drain current (ID) directly in the extraction method of threshold voltage. Some common methods listed underneath are briefly discussed below.
This method determines VTH as the gate voltage for an arbitrary critical drain current (IDCRITICAL) value [
IDCRITICAL referred in Equation (1) is designated such that VTH is on the transition point of linear-sub-threshold region of the device [
Implementation of CCM on Test Device
The technique was implemented on our test device square-sized NMOS with 10-nm technology node and was repeated in similar conditions on other sub 45-nm technology nodes.
The outcome of the results was as follows:
Diffusion current governs the total current in sub-threshold region whereas drift current dominates in strong inversion region. This DDEM process states that by applying low drain voltage (VDS ≈ 0.1 V), the threshold voltage is the distinctive gate voltage at which the condition IDRIFT = IDIFFUSION holds true [
where IDrift and IDiffusion represent the drift current and diffusion current respectively.
Implementation of DDEM on Test Device
The technique was implemented on the test device.
The outcome of the result was as follows:
The DDEM process has the restriction of low biased VDS = 0.1 V. Since the device is always made to operate in linear region, hence the saturation region threshold voltage VTSAT could not be calculated.
These methods use the derivative or the higher order derivate of the drain current value in the extraction method of threshold voltage. Fundamental VTH extraction methods using this respective technique are briefly discussed below.
In this LEM technique, we determine the VTH of the transistor using transconductance (gm) and IDS-VGS curve. The gm is defined as the derivative (slope) of ID-VGS relationship. The extreme gm obtained on the ID-VGS characteristic curve is used to extrapolate the gate voltage (VGS) as shown in
This LEM process provides clear steps for VTH assessment but it is partial to linear region of operation i.e. for low values of VDS. Maximum gm point is not obtainable for higher values of VDS. Furthermore, the DIBL effect also comes into picture for higher VDS and diminishes effective VTH values. Apart from these issues, this method also lacks to determine a constant VTH as dissimilar methods used for attaining maximum gm values. gm also depends on SCEs such as velocity saturation, overlap variations, extrinsic resistance, channel length modulation and so on. This reliance of gm and critical point of maximum gm is tough to accurately model. Henceforth, this produces loopholes in this process to precisely evaluate the VTH.
Implementation of LEM on Test Device
The technique was implemented on the test device.
The outcome of the result was as follows:
As described above, the Maximum gm is not obtainable for higher values of VDS. Hence special efforts were made to calculate VTSAT using this method.
Technique named Quadratic Extrapolation Method (QEM) is also called as “Linear Extrapolation in Saturation Region”. It is used to calculate threshold voltage using LEM in saturation region (VTSAT). As mentioned in LEM, the ID for linear region is proportional to (VGS − VTH). Similarly, ID in saturation region is proportional to (VGS − VTH)2 as shown in Equation (4):
Hence VTSAT can be extracted by extrapolating the curve
Implementation of QEM on Test Device
The technique was implemented on the test device.
The outcome of the result was as follows:
The second-derivative method (SDM), formerly entitled as transconductance change method [
The execution of this SDM process in the linear region is extremely sensitive to
measurement error and noise, as the second derivative amounts to applying a high-pass filter to the measurement [
Implementation of SDM on Test Device
The technique was implemented on the test device. The process was widely affected by noise. Special possessions of filtration and smoothening of curve were considered to extract the correct output as shown in
The outcome of the result was as follows:
In this TDM process, it has been proposed that the VTH can be extracted from the value
of VGS at which the third derivative of the current ID (i.e.,
Implementation of TDM on Test Device
The technique was implemented on the test device. The method was vastly affected by the investigational noise. Hence it was challenging to extract the threshold values. Special properties of smoothening and filtration of the curve were considered to extract the correct output. Even after high considerations, it was observed that VTLIN value was lower than VTSAT value which is commonly unusual.
The outcome of the result was as follows:
The CsrTR method formerly called as Ghibaudo Method (GM) was developed to dodge the extracted VTH value dependence on mobility degradation and parasitic series resistance [
The GM technique, also occasionally called as ‘‘the modified Y function method’’, has been freshly enhanced for application to contemporary devices using a more universal mobility degradation model.
The VTH is extracted from the intercept of the GM versus VGS linear fit.
Implementation of Ghibaudo Method (GM) on Test Device
The technique was implemented on the test device. Non-linearity in the curve caused difficulties in extrapolation process to estimate the required values.
The outcome of the result was as follows:
This method is based on calculating TCR as the ratio of transconductance to the drain current as described in Equation (6) [
It states that the threshold voltage can be determined as the value of VGS where TCR presents its maximum negative slope i.e. VGS corresponding to the minimum value of curve dTCR/dVGS. However, considering TCR by itself significantly increases random tentative noise, specifically in weak inversion.
Implementation of TCR Method on Test Device
The technique was implemented on the test device. The method was highly affected by the investigational noise as seen in
and VTSAT respectively. Hence it was challenging to extract the threshold values. Filtration and smoothening of the curve like properties were applied to extract the correct output. Even after high considerations, it was observed that VTLIN value was lower than VTSAT value which is generally unusual.
The outcome of the result was as follows:
These methods use the integral of the drain current value in the extraction method of threshold voltage. Prevalent VTH extraction methods using this technique are briefly discussed below [
This TM technique was stimulated by the properties of the integral difference function D(V,I), which had been formerly defined for two-terminal device as [
As shown in Equation (7), this function presents the advantageous features of eradicating the effect of any linear element (resistance) coupled in series with the device. To extract VTH, the drain current is constantly measured from below the expected value of VTH versus VGS with a small constant drain voltage (VDS ≈ 100 mV). Subsequently, the succeeding function TM is numerically calculated from the measured data:
where VG0 represents the lower limit of integration analogous to a gate voltage well below threshold in Equation (8). Usually chosen VG0 = 0. The logic of the method is based on the ideal case of a MOSFET, piecewise modelled as: ID = ILEAKAGE for VGS < VTH and ID is proportional to VGS for VGS > VTH. Using the previous streamlining supposition, we observe that:
1) Function TM presents a discontinuity at VTH;
2) TM = −VGS for VGS < VTH; and
3) TM = +VTH for VGS > VTH.
Since for a real device such simplifying conventions are apparently not precisely true, function TM will present an extreme value due to the mobility degradation and its value will be close to VTH.
A plot of TM versus VGS or ln(ID) should result in a straight line below threshold, where the current is dominated by diffusion and is principally exponential. As soon as VGS = VTH, the function TM should vitiate due to mobility degradation. The specified logic accords with the test device as shown in
Implementation of TM Process on Test Device
The technique was implemented on the test device. Smooth curves were obtained. Hence it was easy to extract the threshold values. The VTLIN value and VTSAT value can also be extracted through the TM versus ID curve using the same procedure. On implementation of the mentioned logic, we got the same agreeing values of the threshold voltages.
The outcome of the result was as follows:
The NMID method was initially developed by He and co-workers in 2002 and it was also stimulated by the integral difference function NMID [
Consequently, a plot of NMID versus VGS will characterize a maxima at VGS = VTH.
Implementation of NMID Process on Test Device
The technique was implemented on the test device. Smooth curves were obtained. Flat curves of NMID to evaluate NMID max was challenging to extract the analogous threshold values.
The outcome of the result was as follows:
The NRH method can also be labelled as “Improved NMID Method”. Eliminating the ‘‘1’’ term and the factor ‘‘2’’ from NMID Equation (11), and considering that ID ≠ 0 at VGS = 0, yields a normalized version of the NRH function originally proposed in 2001 for extracting the threshold voltage of amorphous thin film MOSFETs, and later revised in 2010 to evaluate the sub-threshold slope of MOSFETs. Mathematically, the H function is represented as follows [
where ID0 is the drain current at VGS = 0. Limit of the integral can be considered as 0 to VGS in Equation (10). We propose that instead of using H(VGS) function, its reciprocal NRH(VGS) should be used to produce narrow maxima or minima:
A factor of 2 is added to the denominator in Equation (11) to allow a simple graphical explanation of its meaning. The numerator divided by 2 is the area of a triangle with a width of VGS and a height of ID − ID0. Then, NRH is the ratio of this triangle’s area divided by the area under the plot (the integral).
Implementation of NRH Method on Test Device
The technique was implemented on the test device. Smooth curves were obtained. Flat curves of NRH to evaluate NRH max was challenging to extract the analogous threshold values.
The outcome of the result was as follows:
In view of TCR, the differential value of ID by itself expressively increases experimental noise, specifically in weak inversion, an analogous function for low gate bias. The plot of dRH/dVGS versus VGS exemplifies the above statement as it can be clearly seen in
where RH is the reciprocal of function H predefined in NRH method; ID0 is the drain current flow at VGS = 0. Limits of the integral can be considered as 0 to VGS. It is anticipated that the RH function could also be used to extract the threshold voltage. The VTH can be extracted from the maximum negative gradient of the function RH i.e. VGS = VTH analogous to the minimum value of curve dRH/dVGS.
Implementation of RH Method on Test Device
The technique was implemented on the test device. The method was highly affected by the investigational noise. Hence it was challenging to extract the threshold values. As seen in
The outcome of the result was as follows:
These methods use the self-extracting techniques and circuits to extract the value of threshold voltage. Couple of methods under this category are briefly discussed below.
A substantially enhanced HSPICE feature that extracts MOSFET threshold voltage (VTH) based on the constant-current definition universally adopted by fabrication labs to measure, specify, and monitor VTH. Introduced in the 2009.09 release, HSPICE simulations compute constant-current VTH the exact same way VTH is measured in the fab [
For extracting VTH, the “.OPTION IVTH” command is available. This .OPTION IVTH feature is supported for Levels 54 (BSIM4), 69 (PSP100), and 70 (BSIMSOI4) MOSFET models along with latest PTM nano-MOSFET models. It shows acceptable results. This command extracts VTH using CCM and eliminates the use of IDCRITICAL. LX142 model accessible in HSPICE, presents the output results as VTH. Therefore, for short channel devices this process appears effectual in extracting VTH and also shows compatibility with the existing transistor models.
The HSPICE Command “.OPTION IVTH” was implemented on the test device. LX142 model accessible in HSPICE, presents the output results as VTH.
The outcome of the result was as follows:
This proposed ATEC method implements the most popular industrial extraction algorithm (LEM) of biasing a saturated MOSFET to the linear portion of its
Few other similar ATEC designs with different implementation logics are also proposed to extract the VTH.
Implementation of ATEC Method on Test Device
The technique was implemented on the test device. The bulk driven 10 nm nano- NMOS model was used to simulate the circuit. The test device is made to work in linear region. Hence the outcome will be the threshold voltage in linear region (VTLIN). The transient analysis of the circuit gave the following results as shown in
Under this grouping, the VTH is extracted by determining either the deviation of the value or the difference between the measured values. Couple of methods using this logic are listed in this category and are briefly discussed below [
Match-Point method was proposed in 1990 by B. El-Kareh and co-workers. This scheme subjectively evaluates VTH at the value of VGS at which the exponential subthreshold current semi-log extrapolation diverges by 5% from the measured ID.
This MP method exaggerates the weak inversion region neglecting strong inversion.
and saturation region our test device producing an apparent VTH value VTLIN of 0.51 V and VTSAT of 0.52 V respectively. Of course, diverse values of VTH could be arbitrarily achieved by defining the deviation of the extrapolation at threshold at other values different from 5%. The shape of the semi-log curve may be swayed by the presence of parasitic resistance and other SCEs. This method is seldom used as it is more laborious and time consuming.
Implementation of MP Method on Test Device
The technique was implemented on the test device. Generally Match Point method is used to calculate threshold Values by plotting ID versus VGS curve with low biased drain terminal. Hence outcome is VTLIN. The results are extracted by using the semilog plot. We propose to calculate VTSAT by plotting
The outcome of the result was as follows:
In this VVD method, a new interpretation of the threshold voltage is presented as [
The method is implemented by performing the transient analysis on the testing device. In other words, it states that VTH can be extracted by the voltage difference between the constant VG and VS at the normalized current in the ID-VS curves. As seen in
Implementation of VVD Method on Test Device
The technique was implemented on the test device.
results of the VVD circuit. The circuit was compiled and simulated using SPICE. The circuit was analysed using predictive technology model (PTM) at 10-nm, 16-nm, 22-nm, 32-nm, and 45-nm technology node. The input gate voltage was set as 0.9 V. The Vdd was given as constant DC supply of 0.9 V. The multiple values of Load Capacitances (Cload) were used for the testing purpose, however, the VTH extraction results had negligible effect of the variations in the value. Transient analyses were performed on the compiled circuit to extract the threshold voltage value.
The outcome of the result was as follows:
The transient results gave the Vout value marginally equal to Vin, slightly a bit millivolts lower than Vin. Hence, as per the above mentioned logic of the referred extraction method, the calculated VTH is a very small value in millivolts which was not in accord with other extraction method outcomes. The extracted threshold voltage value also seems to be unrealistic. Hence we can accomplish that the VVD extraction method is considerably ineffective at nano-meter technology node.
Under this category, the HEM process uses multiple recognized schemes to extract VTH and combines the advantage of each. One of the hybrid extraction methods is explained below [
This Hybrid extraction method overwhelms the constraints of above mentioned extraction techniques and compute VTH for all values of VDS. It syndicates both methods namely CCM and LEM mentioned beforehand to appropriately extract the VTH. Additionally, this method is also unaffected by the arbitrary value of IDCITICAL. For valuation of VTH using this method first the value of VTH for low biased VDS is attained using LEM (see
Implementation of Hybrid Extraction Method on Test Device
The HEM technique was implemented on the test device. VTLIN was calculated using LEM for ID versus VGS graph with low biased VDS, and correspondingly the IDCRITICAL was also evaluated. Furthermore, ID versus VGS graph is plotted with high biased VDS. Implementing the CCM technique on the plot by using the pre-calculated IDCRITICAL, we are able to calculate VTSAT. Hence we are able to extract VTLIN and VTSAT using Hybrid extraction method as seen in
The outcome of the result was as follows:
All the predefined threshold voltage extraction methods were investigated and implemented at 10-nm Technology node and other sub 45-nm technology node. All the results are verified by extensive 2-D TCAD simulation and confirmed analytically. Various predictive technology models developed by the Nanoscale Integrations and Modelling (NIMO) Group at Arizona State University (ASU) were used to illustrate the characteristics of nano-MOSFETs. The models possess the competency to support short
channel effects, the gate leakage effects and various other second order effects to predict the realistic output.
The results are tabulated in
Noise analysis of the Resistive load Inverter were performed using various VTH extraction method values. Resistive load inverter is one of the most fundamental circuits of MOS family. It characterizes the basic operation of all static gates. With Load resistor (RL) in series with driver NMOS transistor, it has one input connected to the gate of NMOS and one output port connected to the drain terminal of the NMOS as shown in
Noise margin is the limit of noise that a circuit can endure without compromising the operation of circuit. It assures that logic “1” with finite noise added to it, is still recognized as logic “1” and not logic “0” and vice versa. It is principally the difference between
METHOD | 10-nm TN | 16-nm TN | 22-nm TN | 32-nm TN | 45-nm TN | |||||
---|---|---|---|---|---|---|---|---|---|---|
VTLIN | VTSAT | VTLIN | VTSAT | VTLIN | VTSAT | VTLIN | VTSAT | VTLIN | VTSAT | |
CCM | 0.355 | 0.104 | 0.463 | 0.369 | 0.479 | 0.425 | 0.440 | 0.396 | 0.433 | 0.403 |
DDEM | 0.44 | N.A | 0.45 | N.A | 0.47 | N.A | 0.46 | N.A | 0.45 | N.A |
LEM | 0.683 | N.A | 0.719 | N.A | 0.706 | N.A | 0.653 | N.A | 0.634 | N.A |
QEM | N.A | 0.381 | N.A | 0.535 | N.A | 0.564 | N.A | 0.526 | N.A | 0.522 |
SDM | 0.675 | 0.437 | 0.7 | 0.6 | 0.675 | 0.6 | 0.649 | 0.552 | 0.626 | 0.578 |
TDM | 0.559 | 0.363 | 0.65 | 0.504 | 0.65 | 0.525 | 0.595 | 0.5 | 0.578 | 0.5 |
GM | 0.59 | 0.51 | 0.645 | 0.575 | 0.645 | 0.56 | 0.6 | 0.525 | 0.6 | 0.5 |
TCRM | 0.65 | 0.5 | 0.675 | 0.6 | 0.675 | 0.625 | 0.625 | 0.6 | 0.6 | 0.575 |
TM | 0.645 | 0.5 | 0.65 | 0.575 | 0.675 | 0.575 | 0.625 | 0.525 | 0.6 | 0.513 |
NMID | 0.625 | 0.65 | 0.625 | 0.65 | 0.625 | 0.65 | 0.6 | 0.625 | 0.575 | 0.6 |
NRHM | 0.625 | 0.65 | 0.65 | 0.675 | 0.65 | 0.675 | 0.6 | 0.625 | 0.575 | 0.6 |
RHM | 0.675 | 0.675 | 0.7 | 0.725 | 0.725 | 0.725 | 0.675 | 0.7 | 0.65 | 0.675 |
SPICE | 0.30 | 0.19 | 0.34 | 0.23 | 0.42 | 0.37 | 0.43 | 0.38 | 0.43 | 0.40 |
ATEC | 0.61 | N.A | 0.63 | N.A | 0.63 | N.A | 0.62 | N.A | 0.61 | N.A |
MPM | 0.7 | 0.55 | 0.7 | 0.625 | 0.7 | 0.675 | 0.65 | 0.675 | 0.65 | 0.675 |
VVD | N.A | 0.003 | N.A | 0.003 | N.A | 0.003 | N.A | 0.003 | N.A | 0.003 |
HEM | 0.67 | 0.55 | 0.675 | 0.6 | 0.67 | 0.61 | 0.61 | 0.56 | 0.58 | 0.56 |
signal and Noise value. Logically, the reference terms related Noise Margin analysis are described as below (Ref.
・ VOH: (Voltage Output High Value). VOH = Vdd because when the input voltage drops below VTH of the inverter, no current flows. No current flow in turn means no voltage drop across the load resistor and VOUT = Vdd = VOH.
・ VOL: (Voltage Output Low Value). If the input is driven to VOL = Vdd, then the driver NMOS transistor is “ON” and since (Vgs − Vt) > Vds, it is operating in linear mode. The VOUT will be at VOL and the VIN will be at VOH.
・ VIH: (Voltage Input High Value). When VIN = VIH, the output is at VOL and the NMOS is in the linear region.
・ VIL: (Voltage Input Low Value). To determine noise margin we need VIL which is one of two points where we have unity gain. When input low, output high and NMOS in saturation.
Considering the output characteristics of a resistive load inverter; the threshold voltage of the NMOS (VTH) plays a significant role in determining the shape of the voltage transfer characteristic (VTC) of a resistive load inverter. The VTH appears as a critical parameter in expressions for VOL, VIL, and VIH. VOH is determined primarily by the power
supply voltage Vdd. The adjustment of VOL receives primarily attention than VIL, VIH. Larger VTH results in smaller VOL resulting in larger transition slope and higher voltage swing as it can be perceived through
Ideally, when input voltage is logic “1”, the output voltage is expected to be at logic “0”. Hence, VIH is Vdd, and VOL is 0 V as shown in
・ NML (Noise Margin Low)
・ NMH (Noise Margin High)
Practically the situation is not identical. It is observed that due to number of secondary effects like voltage droop, ground bounce, internal resistances, practices, etc.; VOH is slightly less than Vdd i.e.
・ NML (Noise Margin Low)
・ NMH (Noise Margin High)
Hence, if input voltage (VIN) lies somewhere between VOL and VIL, it would be detected as logic “0”, and would result in an output which is acceptable. Similarly, if input voltage (VIN) lies between VIH and VOH, it would be detected as logic “1” and would result in an output which is acceptable.
Application of the extraction methods were implemented to calculate the Noise Immunity and Noise Margins for Resistive Load Inverter using 10-nm test device with Load Resistance RL = 100 Ω and Vdd = 1 V. Referring to
・ We observe that with the increase in the Threshold voltage extraction value, the NMH decreases and NML increases. For an Ideal Inverter, Noise Margins should be equal. Using QEM method for VTH extraction, we obtain the most optimistic results (NMH ≈ NML) in this regards. (Ref.
・ Using “.OPTION IVTH” command accessible in SPICE extraction method for VTH extraction, we obtain the maximum output voltage swing i.e. VOH − VOL for resistive load NMOS inverter (Ref.
・ In the well-designed inverter, the Threshold value of the circuit (Vin = Vout) is nearly equal to Vdd/2. We obtain the flawless results in this regards using CCM extraction method (Ref.
METHOD | VTH | NMH | NML | ∆Vout (VOH-VOL) | ∆NM |NMH-NML| | VTH(Inverter) (Vin = Vout) |
---|---|---|---|---|---|---|
CCM | 0.355 | 0.4325 | 0.3440 | 0.9687 | 0.0885 | 0.498 |
DDEM | 0.44 | 0.3475 | 0.4242 | 0.9638 | 0.0767 | 0.572 |
LEM | 0.683 | 0.1045 | 0.6364 | 0.9331 | 0.5319 | 0.779 |
QEM | 0.381 | 0.4065 | 0.3687 | 0.9674 | 0.0378 | 0.521 |
SDM | 0.675 | 0.1125 | 0.6303 | 0.935 | 0.5178 | 0.771 |
TDM | 0.559 | 0.2285 | 0.5329 | 0.9536 | 0.3044 | 0.675 |
GM | 0.59 | 0.1975 | 0.5602 | 0.9498 | 0.3627 | 0.701 |
TCRM | 0.65 | 0.1375 | 0.6106 | 0.9403 | 0.4731 | 0.751 |
TM | 0.645 | 0.1425 | 0.6066 | 0.9412 | 0.4641 | 0.746 |
NMID | 0.625 | 0.1625 | 0.5900 | 0.9447 | 0.4275 | 0.73 |
NRHM | 0.625 | 0.1625 | 0.5900 | 0.9447 | 0.4275 | 0.73 |
RHM | 0.675 | 0.1125 | 0.6303 | 0.935 | 0.5178 | 0.771 |
SPICE | 0.30 | 0.4875 | 0.2915 | 0.9712 | 0.196 | 0.449 |
ATEC | 0.61 | 0.1775 | 0.5774 | 0.947 | 0.3999 | 0.718 |
MPM | 0.7 | 0.0875 | 0.6489 | 0.9286 | 0.5614 | 0.793 |
HEM | 0.67 | 0.1175 | 0.6265 | 0.9362 | 0.509 | 0.767 |
・ The slope of the output curve within the transition region describes the propagation delay properties of the circuit. The variation in the VTH had a negligible effect on the slope of the curve resulting in nearly persistent switching characteristics for most of the extraction methods.
We presented, reviewed and critically compared several extraction methods currently used to determine the threshold voltage of bulk driven MOSFETs at 10-nm technology node and other various sub 45-nm technology nodes for precise evaluation of the respective method. The relative performance of all the methods was illustrated and compared under similar conditions by applying them to the test devices: bulk driven nano-MOSFETs with 10-nm technology node along with other various sub 45-nm technology nodes. We can perceive that the extracted threshold voltage largely depends on the method used for extraction specifically at nano-scale. The CCM has an ambiguous definition on the critical drain current (ID0) contingent on technology being used. The LEM, QEM and TM outcomes are affected by extrinsic resistance effects, mobility degradation, Short Channel Effects and other second order present effects. SD, TD, GM, RH and TCRM are also widely affected by noise and are also not based on ideal threshold voltage definition condition. The MP is seldom used as 5% deviation value gives an ambiguous definition of threshold. The VVD extraction method is considerably ineffective at nano-meter technology node. In NMID and NRH, the correct calculation of maxima in wide ranges makes the extraction task much more difficult. We can also infer number of facts and properties from noise margin analysis performed using various threshold extraction methods. QEM provides the most optimistic balanced noise margin results. The maximum output voltage swing was observed using SPICE extraction method. CCM delivers the most appropriate results in calculating Threshold value of the circuit. The above listed features and properties of various extraction methods can be helpful in merging the threshold voltage compact models at nano-level technology nodes.
Swami, Y. and Rai, S. (2016) Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node. Circuits and Systems, 7, 4248- 4279. http://dx.doi.org/10.4236/cs.2016.713349