This paper presents the design and implementation of a Stepper Motor using Nexys2 circuit board based on a Xilinx Spartan 3E Field Programmable Gate Array (FPGA) device with VHDL code. The algorithm implemented on FPGA allows a substantial decrease of the equivalent processing time developed by different velocity controllers. The Stepper Speed control is achieved using VHDL code, and the hardware digital circuit is designed for a programmable rotational stepper motor using VHDL as a tool and FPGA as a target technology. The 50 MHZ provided by the starter kit is divided to obtain the necessary delay time between the motor phases that ranges between 2 - 10 m seconds. Though output selections, the direction of rotation of the stepper motor besides the magnitude of the angle of movement and the rotation speed can be controlled. The major advantage of using reconfigurable hardware (FPGA) in implementing the Stepper Motor instead of a discrete digital component is that it makes modifications to the design easy and quick and also, the total design hence represents an embedded system (works without computer). The total programmable hardware design that controlled on the stepper motor movement, occupied an area that did not exceed 12% of the chip resources.
A stepper motor is an electrically powered motor that creates rotation from electrical current driven into the motor. Physically, stepper motors can be large but are often small enough to be driven by current on the order of milliampere. Current pulses are applied to the motor, and this generates discrete rotation of the motor shaft [
Stepper motor is used in broad application for speed and position control. In this paper, the speed profile of stepper motor is analyzed based on Field Programmable Gate Implementation (FPGA). As a speed moving motor, it must have rising and falling process which includes missing steps by steps. FPGA gives the different control method for controlling the speed of stepper motor
To avoid missing steps, the system based on FPGA has good interfacing, thus we can interface more than one stepper motors for further application [
There are three basic stepper motor types. They are:
・ Variable-reluctance
・ Permanent-magnet
・ Hybrid.
The stepper motor shown in
When different phase coils are powered the motor will move a very small amount, and if you change quick enough then smooth rotation can be achieved [
In designing and implementing the Stepper Motor using FPGA, a Nexys2 circuit board based on a Xilinx Spartan 3E Field Programmable Gate Array (FPGA) device with VHDL code is used which is the controller as shown in
In this design, the inputs to the FPGA and the Pmod pins location as shown in
NET "clk50M" LOC = B8
The clk50M pin connects to a 50 MHz clock on the FPGA development board. It is this clock signal that co-ordinates all activities on the FPGA. The period of this signal should be specified, so that the tools can make sure that all of the design’s logic functions correctly at this speed (as the design is limited by the switching speed of the FPGA’s logic and the speed at which signals propagate across the chip). Note the clk50m Pin is connected to B8 on the FPGA [
NET "sw_dir" LOC = "H18";
NET "sw_enable" LOC = "G18";
NET "sw_speed" LOC = "K18";
The “sw_” signals are connected to the switches which equally serve as the input to the FPGA.
"sw_dir" LOC = "H18"; this is the input switch that coordinate the direction of the motor either to rotate to the left when the signal is high “1” or to rotate to the left when the signal is low “0”. Note the sw_dir Pin is connected to H18 on the FPGA.
"sw_enable" LOC = "G18"; this is the input switch that enable or powered the motor to start operation when the signal is high “1” or disable or stop the motor operation when the signal is low “0”. Note the sw_enable Pin is connected to G18 on the FPGA.
"sw_speed" LOC = "K18"; this is the input switch that coordinate or adjust the speed of the motor by increasing the speed as specified in the VHDL code/ program when the signal is high “1” or reduce the speed when the signal is low “0”. Note the sw_speed Pin is connected to K18 on the FPGA.
Also, the outputs of the FPGA as designed are narrated below.
NET "phase_a" LOC = "L15";
NET "phase_b" LOC = "K12";
NET "phase_c" LOC = "L17";
NET "phase_d" LOC = "M15";
NET "position<0>" LOC = "J14";
NET "position<1>" LOC = "J15";
NET "position<2>" LOC = "K15";
NET "position<3>" LOC = "K14";
NET "position<4>" LOC = "E17";
NET "position<5>" LOC = "P15";
NET "position<6>" LOC = "F4";
NET "position<7>" LOC = "R4".
On the FPGA board “phase_” signals are connected to the PMOD connector, the “position” signals are connected to the LEDs.
"phase_a" LOC = "L15";
"phase_b" LOC = "K12";
"phase_c" LOC = "L17";
"phase_d" LOC = "M15".
These phase_a thru d are the outputs from the FPGA through the PMOD interface JA and connected to the Stepper Motor through the Motor driver as shown in
Also, the “position” signals are connected to the LEDs on the Board with their corresponding pin locations.
NET "position<0>" LOC = "J14";
NET "position<1>" LOC = "J15";
NET "position<2>" LOC = "K15";
NET "position<3>" LOC = "K14";
NET "position<4>" LOC = "E17";
NET "position<5>" LOC = "P15";
NET "position<6>" LOC = "F4";
NET "position<7>" LOC = "R4".
The speed for a reactive motor is given by the formula
where f is the pulse frequency;
The pulse frequency changes due to fluctuations in the environmental conditions. Thus a fixed number of step-by-step operations are done in every week so that the step error will not accumulate and change the pulse frequency. In actual position of stepper motor control, we must inevitably face the issue of speed. To avoid the lost step phenomenon the general requirement for the highest operating frequency should be less than (or equal) stepper motor in response to the frequency. This is the operating frequency in which stepper motor can start, stop or reverse rather than out of step phenomenon.
In this paper, the successful implementation of Stepper Motor using FPGA is achieved using Xilinx Spartan 3E Field Programmable Gate Array (FPGA) device and programmed by VHDL code [
During the implementation, the function of the Pmod driver Board as shown in
To analyze the performance of this system, the algorithm was implemented on Xilinx Spartan 3E Field Programmable Gate Array (FPGA) device. A constraints file which defines the input and output signals of the logical design are connected to each pins on the outside of the chip. The chip used is a Ball Grid Array chip, and
pins are located with a letter for the column and a number for the row. In this design we are using 16 pins, but the FPGA has many more available.
There is one special pin, the clk50M pin, which connects to a 50 MHz clock on the FPGA development board. It is this clock signal that co-ordinates all activities on the FPGA. The period of this signal should be specified, so that the tools can make sure that all of the design’s logic functions correctly at this speed (as the design is limited by the switching speed of the FPGA’s logic and the speed at which signals propagate across the chip). This design has three internal signals, and that also act as registers (they “hold” values). The “coils” is initialized to “0011” as it will be connected to the output of the design that powers the stepper motor, and coils A and B will be initially powered. The sizes of these signals have been carefully chosen = coils has to hold the four outputs for the stepper motor, count has to hold number to 400,000 and step count has to hold the position to be indicated on the eight LEDs.
that shows the amount of resources usage for the Stepper Motor implementation using FPGA. The design has been compiled down into a “.bit” file that is used to program the FPGA, and the tools provide a usage report that shows what physical resources have been consumed. In this case we use 34 of 4656 logic slices, not even 1% of the chip: this shows how effective and less resource usage is been achieve when implemented with FPGA. Below are some other benefits of using FPGA in this Stepper Motor implementation [
1) Performance―The hardware parallelism nature of FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle. Controlling inputs and outputs (I/O) at the hardware level provides faster response times and specialized functionality to closely match application requirements. This design is then compiled down into a “.bit” file that is used to program the FPGA. The tools provide a usage report that shows what physical resources have been consumed. In this case we use 34 of 4656 logic slices. Not even 1% of the chip. This again evaluates and validates the parallelism nature of FPGA which was equally achieved during our design due to small amount of resources used on the FPGA and the execution time is faster.
2) Reliability―Processor-based systems often involve several layers of concept to help schedule tasks and share resources among multiple processes. For any given processor core, only one instruction can execute at a time, and processor-based systems are continually at risk of time-critical tasks preempting one another. Because FPGAs do not use OSs, it minimizes reliability concerns with true parallel execution and deterministic hardware dedicated to every task. This was proven when all our codes instructed were executed using VHDL at the same time on the FPGA.
3) Long-term maintenance―As earlier discussed, FPGA chips are field-upgradable and do not require the time and expense involved with ASIC redesign. Due to reconfigurable nature of FPGA chips, it can keep up with future modifications that might be necessary. As a product or system matures, you can make functional enhancements without spending time redesigning hardware or modifying the board layout. During our design, we changed the configuration many times so as to drive our stepper Motor and do not incur any additional cost due to its programmability nature.
4) Cost―The nonrecurring engineering (NRE) expense of custom ASIC design far exceeds that of FPGA- based hardware solutions. With FPGA, it means that you have no fabrication costs or long lead times for assembly. This is because system requirements often change over time, the cost of making incremental changes to FPGA designs is negligible when compared to the large expense of re-designing an ASIC. In our design and implementation, the cost of the SPARTAN 3E FPGA Board is really small as compared to other processors like dSPACE in implementation of the same project.
The result has verified an easy way to design and implement a Stepper Motor using FPGA which equally guarantees an effective speed control with less resources usage. Due to the system architecture and its parallelism nature, one FPGA can drive more than one motor without increasing the processing time. The algorithm implemented on FPGA allows a substantial decrease of the equivalent processing time develop by different velocity controller. The Stepper Speed control is achieved using VHDL code. This fast prototype and implementation of Stepper Motor proves the effectiveness and programmability features of FPGA in the industrial at large.
Warsame H. Ali,Emmanuel S. Kolawole,Pamela Obiomon,John H. Fuller,Shukri Ali,Penrose Cofie, (2016) Rapid Prototype with Field Gate (A Design and Implementation of Stepper Motor Using FPGA). Circuits and Systems,07,1392-1403. doi: 10.4236/cs.2016.78122