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This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconductance efficiency and low gate bias condition. The top resistive biasing has more benefit with the feature of phase noise than MOS current source since it can support the low-noise characteristics and large output swing. The LC-VCO designed in 130-nm CMOS process with 0.7-V supply voltage achieves phase noise of -116 dBc/Hz at 200 kHz offset with tuning range of 398 MHz to 408 MHz covering medical implant communication service (MICS) band.

Integrated LC oscillators are important building blocks in the implementation of radio frequency (RF) front-end modules to provide a stable local oscillator (LO) signal for modulation/demodulation or up/down frequency conversion. RF transceivers for implanted medical device require miniaturized forms with low-power consumption and fully integration. The medical implant communication service (MICS) band in the frequency range of 402 MHz to 405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics in human body and are well suited for achieving a good trade-off between size and power. Furthermore, the use of MICS band does not pose a significant risk of interference to other frequencies within or close to this band. The phase noise requirement for an oscillator operating in MICS band is less than −100 dBc/Hz at 200 kHz offset frequency [

One of the major challenges in the design of RF front-end modules is implementation of fully integrated low- power, low-phase-noise voltage-controlled oscillators (VCOs). The CMOS devices operating in subthreshold region have an advantage of higher transconductance to power dissipation ratio with decent noise performance in comparison with the strong inversion region. Therefore, the subthreshold VCO achieves low-power and low-phase-noise characteristics. The circuits designed with MOS transistors biased in the subthreshold region operate with lowered voltage headroom, resulting in lower supply voltage. However, the phase noise performance is degraded due to the small amplitude at low supply voltages and it is recognized that the active current source for biasing purpose introduces noise performance degradation [

This paper presents the analysis of phase noise performance through various biasing techniques, and a low- phase-noise LC-VCO is designed using resistive biasing instead of active current source scheme. The top resistive biasing is employed for low-phase-noise and low-voltage operation because of its inherent advantage of low effective noise and large voltage swing. This circuit has been designed in 130-nm CMOS technology with 0.7-V supply voltage. This paper is organized as follows. Section 2 presents the phase noise analysis in accordance with various biasing techniques. Section 3 describes the circuit design, and presents the simulation results. Finally, conclusions are drawn in Section 4.

There are many ways to realize the integrated LC-VCOs. For the analysis of the current biasing techniques, an NMOS cross-coupled differential pair is used for the core oscillator design, which has an advantage of common-mode noise suppression and low-voltage operation. The different cases of current biasing techniques in differential LC-VCO are shown in

The phase noise in harmonic oscillators based on the linear time-variant (LTV) analysis approach is expressed as [

where _{T} is the oscillation amplitude across the LC resonator, and the effective noise power

where T_{p} is the oscillation time period,

generated by the i-th device, and _{T} is given by

where _{T} is the equivalent parallel resistance of the LC resonator. Among the components of LC resonator, Q factor of inductor is more dominant than of capacitor because inductor has lower Q factor than that of capacitor. So, R_{T} can be calculated as

where _{L} is the Q factor of inductor. This is the reason that the usual design practices try to maximize both the available oscillation amplitude and the Q factor in order to reduce the phase noise. Also, the effective noise power proportionally links the phase noise performance and has relevance to the noise source which depends on the biasing techniques.

Lower effective noise improves phase noise performance, and it depends on the noise source. The total effective noise of LC-VCO using MOS current source (

where_{1} and M_{2} in the case of MOS current source. In this work,

To reduce the noise from the MOS current source, a low-value resistor is employed as a practical biasing technique for LC-VCOs. In the case of using a resistor as current source, the thermal noise caused by MOS current source can be replaced by the thermal noise of the bias feeding resistor. Here, considering the differential- pair MOS switching action in resistive biasing case, the total effective noise for LC-VCO using resistive biasing (

where

asing position (top and bottom), and _{1} and M_{2} in the case of resistive biasing. The value of

From the discussion in the above section, increasing oscillation amplitude reduces the phase noise. In Equation (3), the oscillation amplitude in LC-VCO is proportional to the equivalent parallel resistance of the LC resonator R_{T} and bias current

where

gion is proportional to the exponential of the gate-source voltage. The gate-source voltage in bottom biasing is attenuated by the voltage drop across the bottom resistor. The subthreshold drain currents for two resistive biasing have the following relationship

where _{0} is the technology current factor, L and W are the effective channel length and width, V_{TH} is the threshold voltage, n is the subthreshold slope factor, _{T} = 25.9 mV at room temperature). The above equation can explain that the top biasing has more current than bottom biasing as shown in

In this study, the top resistive biasing is applied to design the LC-VCO operating at a 0.7-V supply for the MICS band. The structure of NMOS cross-coupled differential LC-VCO with top resistive biasing is shown in

A low-voltage low-phase-noise LC-VCO operating in subthreshold region using top resistive biasing is presented. The subthreshold-biased LC-VCO achieves low-power consumption, and the lower gate bias provides the phase noise improvement. The LC-VCO using top resistive biasing operates from 398 MHz to 408 MHz and exhibits a phase noise of −116 dBc/Hz at 200 kHz offset frequency with an improvement of 1 dB to 6 dB compared with other biasing techniques in similar conditions. Designed LC-VCO consumes 700 μW from a 0.7-V

supply. In comparison of the biasing techniques, the top resistive biasing has least effective noise power because of the elimination of noisy MOS current source, and has a large output swing because of no current degradation. Therefore, the top resistive biased LC-VCO realizes the low-voltage operation with better phase noise performance.

The IC in this study is designed as part of the chip fabrication program of the VDEC at the University of Tokyo in collaboration with Cadence Design Systems.