Circuits and Systems
 Vol. 3  No. 4 (2012) , Article ID: 23645 , 6 pages DOI:10.4236/cs.2012.34048

Grounded and Floating Inductance Simulation Circuits Using VDTAs

Dinesh Prasad*, D. R. Bhaskar

Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, Jamia Millia Islamia, New Delhi, India

Email: *dprasad@jmi.ac.in, dbhaskar@jmi.ac.in

Received August 14, 2012; revised September 10, 2012; accepted September 17, 2012

Keywords: VDTA; Inductance Simulation; Filters

ABSTRACT

New electronically-controllable lossless grounded and floating inductance simulation circuits have been proposed employing Voltage Differencing Transconductance Amplifiers (VDTA). The proposed grounded inductance (GI) circuit employs a single VDTA and one grounded capacitor whereas the floating inductance (FI) circuit employs two VDTAs and one grounded capacitor. The workability of the new circuits has been verified using SPICE simulation with TSMC CMOS 0.18 μm process parameters.

1. Introduction

Several circuits and techniques for the simulation of grounded and floating inductance employing different active elements such as operational amplifiers, current conveyors, current controlled conveyors, current feedback operational amplifiers, operational mirrored amplifiers, differential voltage current conveyors, current differencing buffered amplifiers, current differencing transconductance amplifiers, operational transconductance amplifiers (OTAs) have been reported in the literature see [1-33] and the references cited therein. Many active elements have been introduced by Biolek, Senani, Biolkova and Kolka in [34], VDTA is one of them. A CMOS realization of VDTA and its filter application have also been reported in [35]. The purpose of this paper is, to propose new electronically-controllable VDTAbased lossless GI and FI circuits employing a grounded capacitor. The GI uses only one VDTA along with a grounded capacitor and does not require any matching condition whereas FI employs two VDTAs, a grounded capacitor and requires matching conditions. The workability of the proposed new circuits has been verified using SPICE simulation with TSMC CMOS 0.18 μm process parameters.

2. The Proposed New Configurations

The symbolic notation of the VDTA is shown in Figure 1, where VP and VN are input terminals and Z, X+ and X– are output terminals. All terminals of VDTA exhibit high impedance values [35]. The VDTA can be described by the following set of equations:

(1)

The proposed grounded and floating inductance circuits are shown in Figures 2 and 3 respectively.

A routine circuit analysis of the circuit shown in Figure 2 results in the following expression for the input impedance

(2)

The circuit, thus, simulates a grounded inductance with the inductance value given by

(3)

which is electronically controllable by either or.

Figure 1. The symbolic notation of VDTA.

Figure 2. Proposed grounded inductance simulation configuration.

Figure 3. Proposed floating inductance simulation configuration.

On the other hand, analysis of the new FI circuit shown in Figure 3 yieldswith and

(4)

which proves that the circuit simulates a floating lossless electronically-controllable inductance with the inductance value given by

(5)

3. Non-Ideal Analysis and Sensitivity Performance

Considering the various VDTA non-ideal parasitics i.e., the finite X-terminal parasitic impedance consisting of a resistance in parallel with capacitance and the parasitic impedance at the Z-terminal consisting of a resistance in parallel with capacitance.

The non-ideal input impedance for the circuit shown in Figure 2 is given by

(6)

From Equation (6) a non-ideal equivalent circuit of the grounded inductor is derivable which is shown in Figure 4.

Where, , , and

From the above, the sensitivities of LGI with respect to various active and passive elements are found to be

, , , (7)

Similarly, for the circuit shown in Figure 3, the input-output current and voltage relationships are given by:

with

and (8)

The non-ideal equivalent circuit of floating inductor of Figure 3 is derivable from Equation (8) and is shown in Figure 5.

where     and

The various sensitivities of LFI with respect to active and passive elements are:

, ,

, (9)

Figure 4. Non-ideal equivalent circuit of Figure 2.

Figure 5. Non-ideal equivalent circuit of Figure 3.

Taking gm1 = gm2 = 631.702 μA/V, Cz = CZ = 0, Rx = Rz = ∞ and C = 0.01nF, these sensitivities are found to be (1, 0, 0, 0, 1, 1) and (1, 0, –1, –1) for Equations (7) and (9) respectively. Thus, all the passive and active sensitivities of both grounded and floating inductance circuits are low.

4. Simulation Results of the New Proposed Grounded/Floating Inductance Configurations

The workability of the proposed simulated inductors has been verified by realizing a band pass filter (BPF) as shown in Figures 6 and 7.

The transfer function realized by this configuration is given by

(10)

from where it is seen that bandwidth and centre frequency both are independently tunable, the former by R1 and the latter by any of the transconductances gm1, gm2 and C2.

The transfer function realized by the configuration shown in Figure 7 is given by

Figure 6. Band pass filter realized by the new grounded simulated inductor.

Figure 7. Band pass filter realized by the new floating simulated inductor of Figure 3.

with

and

(11)

In this case, bandwidth is tunable by R0 whereas centre frequency can be tuned by C0.

Performance of the new simulated inductors was verified by SPICE simulations. CMOS-based VDTA from [35] was used to determine the frequency responses of the grounded and floating simulated inductors. The following values were used for grounded as well as floating inductor: C = 0.01 nF, gm1 = gm2 = 631.7 μA/V. From the frequency response of the simulated grounded inductor (Figure 8) it has been observed that the inductance value remains constant upto 10 MHz. Similarly, from the frequency response of the simulated floating inductor (Figure 9) the inductance value also remains constant up to 10 MHz.

To verify the theoretical analysis of the application circuits shown in Figures 6 and 7, these configurations have also been simulated using CMOS VDTAs. The component values used were for Figure 6: C1 = 5 pF, C2 = 0.01 nF, R1 = 1.58 kΩ and for Figure 7: C0 = 0.01 nF, C1 = 5 pF, R0 = 1.58 kΩ. The VDTAs were biased with ±0.9 volts D.C. power supplies with IB1 = IB2 = IB3 = IB4 = 150 μA. Figures 10 and 11 show the simulated filter responses of the BP filters. A comparison of the other

Figure 8. Frequency response of the simulated grounded inductor.

Figure 9. Frequency response of the simulated floating inductor.

previously known grounded and floating inductance simulators has been presented in Table 1.

Figure 10. Frequency response of BPF using the proposed simulated GI.

Figure 11. Frequency response of BPF using the proposed simulated FI.

Table 1. Comparison with other previously known grounded and floating simulators.

The above results, thus, confirm the validity of the applications of the proposed grounded and floating simulated inductance circuits.

5. Conclusion

New electronically-controllable circuits of lossless grounded and floating inductance have been proposed employing VDTAs. The proposed grounded inductance circuit employs only one VDTA and one grounded capacitor. On the other hand, the floating inductance configuration uses two VDTAs and one grounded capacitor, requires realization conditions for floatation. A comparison of the other previously known grounded and floating inductance simulators has been presented in Table 1. The SPICE simulation results have confirmed the workability of the new proposed circuits.

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NOTES

*Corresponding author.

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