ABSTRACT

The In-doped CdTe/Si (p) heterostruture was fabricated and its electrical and photoelectrical properties were studied and interpreted. During the fabrication processes of CdTe/Si heterojunction, some practical troubles were encountered. However, the important one was the formation of the SiO₂ thin oxide layer on the soft surface of the Si during the formation of the back contact. The silicon wafer was subjected to different chemical treatments in order to remove the thin oxide layer from the silicon wafer surfaces. It was found that the heterojunction with Si (p+) substrate gave relatively high open circuit voltage comparing with that of Si (p) substrate. Also an electroforming phenomenon had been observed in this structure for the first time which may be considered as a memory effect. It was observed that there are two states of conduction, non-conducting state and conducting state. The normal case is the non-conducting state. As the forward applied voltage increased beyond threshold value, it switches into the conducting state and remains in this state even after the voltage drops to zero.

1. Introduction

In recent years much attention had been paid to the heterojunction devices research [1]. The success of heterojunctions is fully established in electronic devices including solar cells high quality lasers, and optical detectors [2]. Heterojunctions which consist of CdTe as one of the junction sides had been under investigation for many years. Mohamed et al. [3] also studied the electrical properties of post-deposition annealed and asdeposited In-doped CdTe thin films, it was observed that the CdTe film was of modified Poole-Frenkel conduction mechanism and the resistivity of the film could be lowered by more than one order of magnitude due to indium doping. Also, considerable amount of work had been paid to develop the CdS/CdTe solar cells over the last ten years [4,5]. Levi [6] also studied the electrical, photo-electrical, and structural properties of CdS/CdTe heterostruture. High efficiency solar cells of efficiencies up to 12.5% were developed with a CdTe low temperature (>450˚C) process [7]. Efficient solar cell performance requires minimizing the forward recombination current and maximizing the light generated current. Collection losses can be minimized in thin film of high absorption and short diffusion length. Voltage dependent photocurrent collection losses in CdTe films were observed [8]. The voltage dependence of photo current of CdTe/CdS solar cells was characterized by separating the forward current from the photocurrent.

2. CdTe/Si Heterojunctions Properties

Mohamed et al. [9] have studied the photovoltaic properties of In-doped CdTe (p) homojunction structure. It was revealed that the In-doped CdTe thin film is of high bulk resistivity, which affects its photovoltaic properties. The deteriorative effect of high bulk resistivity increases by increasing the light intensity which in turn limits the benefit of using higher light intensity that improves the conversion efficiency. A new factor denoted as “S” was devised to measure how the series resistance affects the short circuit current versus light intensity characteristics of the new structure and generalized conclusions were put forward to cover all types of the conventional solar cells. The In-doped CdTe (p) thin film is of high bulk resistivity which largely affects its photovoltaic properties particularly the short circuit current. It was noted that, the deteriorative effect of the high bulk resistivity increases by increasing the light intensity, which in turn limits the benefit of using light concentrators that improve the short circuit current. Birnkmanm and Alamri [10] found that the use of post deposition heat treatment would probably reduce the bulk resistance and possibly improves contact performance. It was proved previously [4] that the polarity of the applied voltage had almost no effect on the I-V characteristics of Al-In doped-CdTe-Al structure annealed at 100˚C, which means that the contacts are ohmic. Variation of bulk resistivity with the diffusion temperature is shown in Figure 1. It can be observed that the bulk conductivity of the doped (diffused) films is about one order higher than that of the undoped CdTe films. This is due to the incorporation of Indium atoms that acts as donor sites, which in turn increases the carrier concentration. This will decrease the barrier height at the grain boundaries, resulting in less impedance to the carrier transport [11]. Also it was found that the maximum bulk conductivity is occurred at 100˚C diffusion temperature.

There is intensive interest to develop high efficiency multi-junction solar cells including the exploration of using silicon (Si) substrate. Heterojunction devices have been realized by depositing phosphorus-doped silicon (Si) (n-type) on a p-type crystalline silicon substrate. The open circuit voltage increases proportionally to the band gap, whereas the number of absorbed photons, i.e., the current decreases with broadening the band gap. The resulting power, as the product of voltage and current, has a maximum value at 1.3 eV. Silicon with the band gap of 1.1 eV and CdTe with 1.5 eV are close to this optimal value. Consistent growth of laterally uniform CdTe (CT) on Si substrate by molecular beam epitaxy has been reported, which indicates that II-VI semiconductor alloys based on CdTe and grown on Si substrates may give good cell performance [12]. Recent nanostructures materials (nanocrystal incorporated in isolators) are used for windows. Electrons can migrate in these structures from one nanocrystal (nc) to adjacent nc and to electrode by tunnel effect, therefore such materials are conductive. Usually nc of the same material as in solar is used for window. Thus, CdTe nc can be used for CdTe solar cell window. Then n-type Si nc on p-type bases is a possible perspective [13].

3. Laboratory Preparation

The samples that will be discussed in this paper are of common evaporation conditions. Few samples of CdTe thin films were prepared by thermal evaporation and deposited on Si substrate. The deposition parameters and the sequence of fabricating In-doped CdTe/Si (p) structure are as follow (see Figure 2):

(a) Deposition of Al back contact 2000 Å on the back surface of the silicon wafer.

(b) Deposition of CdTe layer of 4000 Å thickness (since the photosensitivity of the evaporated CdTe shows a relatively high value at this thickness [14]) with 8 Å/s rate of deposition and at 25˚C substrate temperature. The next step is annealing process at 200˚C (under vacuum) for an hour in order to anneal the CdTe layer and to support back contact formation.

(c) Deposition of indium layer with 100 Å thickness, on top of the CdTe layer followed by Indium diffusion in CdTe by heating process at 100˚C under vacuum for an hour.

(d) and (e) deposition of aluminum or indium top contact.

In this paper different structures will be studied. So, for the sake of simplicity, some symbols will be used so that one can easily recognize the different structures. These symbols will be used as superscript incorporated on the letters that describe different structure layers. For instance, the structure In^*-In^~* CdTe/Si (p) indicates and from right to left that: a silicon wafer (p-type) on which a CdTe layer is deposited, In^~* denotes an indium layer diffused in the CdTe layer in dot-shaped form, so the superscript (^~) represents a diffused layer followed by the superscript (^*) denotes the shape of the diffused layer in dotshaped form. In^* denotes indium top contact in dot-shaped form. In this paper the following superscripts will be used: (^*): denotes a dot shape, (^~): denotes a diffused layer and (^#): denotes a grid shape, usually used for top contacts.

During the fabrication processes of CdTe/Si heterojunction, some practical troubles were encountered. However, the important one is the formation of the SiO₂ thin oxide layer on the soft surface of the Si during the formation of the back contact. The silicon wafer is subjected to different chemical treatments in order to remove the thin oxide layer from the silicon wafer surfaces. Then the sequence of fabrication the on Al-CdTe/Si (p)-Al structure is as follow:

1) Deposition of Al back contact.

2) Formation of the back contact by annealing process at 200˚C for an hour (under vacuum).

3) Deposition of CdTe layer.

4) Deposition of Al top contact.

During the formation of the back contact, a thin oxide layer (SiO₂) is grown undeliberately. The existence of this layer is investigated practically by fabrication of Al-Si-Al structure with back contact formation as in steps 1 and 2 above, after which a top contact Al is deposited. Figure 3 illustrates the (I-V) characteristics of the device, which exhibits a diode effect that consequently indicates the formation of a MOS diode (AlSiO₂-Si-Al). The existence of the oxide layer badly affects the (I-V) characteristics of the structure AlCdTe/Si (p)-Al.

Figure 4 depicts the (I-V) characteristics of the CdTe/Si with the interfacial oxide layer with different CdTe thicknesses. It can be deduced that the characteristics are not of a PN junction (no rectification effect) due to the interfacial oxide layer which prevents the establishment of heterojunction between CdTe and Si. Evidently the introduction of oxide layer increases the total absorption depth. This in turn utilizes the wasted portion of the solar spectrum, consequently increases the short circuit current [15,16].