J. KIEFFER ET AL.
Copyright © 2013 SciRes. CN
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Figure 8. Impact of the different methods on EVM.
where ksyn is still the TDC gain in the synthesis mode
defined in equation (10) and which is now calibrated
before inserting the modulation into the PLL. Then, the
modulation, normalized by the wanted output frequency,
is applied on the TDC gain at each sample. This is the
third inputs of the proposed three-points modulator.
The Figure 8 shows the amelioration of the EVM with
the implementation of this new expression instead of
keeping the TDC gain filtered or constant after calibra-
tion. The PLL is still considered perfect.
Several observations can be made thanks to this figure.
At first, it is useless to increase the TDC gain filtering
bandwidth so that most of the modulation can pass with-
out alterations. On the contrary, the EVM increases with
the bandwidth enlargement.
Then, the proposed solution allows an EVM reduction
of 2% compared to a method where the TDC gain is kept
constant after the same calibration (filtering with 10 kHz-
bandwidth in this case). Moreover, the solution presents
certain robustness regarding a calibration error. In others
words, having an offset on the gain estimation has less
impact on EVM than not adding the modulation.The final
EVM is under 1%, below the EVM with the rest of the
PLL imperfections.
4. Conclusions
A nonlinear Digital PLL model has been developed to
bring out the impact of TDC gain estimation in polar
architectures. This causes indeed a large EVM degrada-
tion for wideband modulations such as WCDMA. The
proposed solution which finally amounts to add the mod-
ulation on the TDC gain transforms the classical
two-points modulator in a three-points modulator and
allows a good reduction of the EVM degradation due to
this contributor. This shows that the phase path is not
straightforward for wideband modulations from the con-
clusions derived from GMSK/EDGE polar modulator.
5. Acknowledgements
The authors thank Samuel Dubouloz for his help on the
modulator and demodulator.
REFERENCES
[1] W. B. Sander, S. V. Schell and B. L. Sander, “Polar
Modulator for Multi-mode Cell Phones,” in Proc. IEEE
Custom Integrated Circuits Conf., 2003, pp. 439-445.
[2] P. Reynaert and M. Steyaert, “A 1.75-GHz Polar Modu-
lated CMOS RF Power Amplifier for GSM-EDGE,”
IEEE SSC, Vol. 40, No. 12, 2005.
[3] M. Perrott, M. Trott and C. Sodini, “A Modeling Ap-
proach for ∑-∆ Fractional-N Frequency Synthesizers Al-
lowing Straightforward Noise Analysis,” IEEE JSSC, Vol.
37, No. 8, 2002.
[4] M. Perrott, “Fast and Accurate Behavioral Simulation of
Fractional-N Frequency Synthesizers and other PLL/DLL
Circuits,” Design Automation Conference, 2002. Pro-
ceedings. 39th.
[5] C. Joubert, J.F. Bercher, G. Baudoin, T. Divel, S. Ramet
and P. Level, “Time Behavioral Model for Phase-Domain
ADPLL based Frequency Synthesizer,” IEEE Radio and
Wireless Symposium, 2006.
doi:10.1109/RWS.2006.1615121
[6] R. B. Staszewski, K. Muhammad, D. Leipold, C.-M.
Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio,
R. Staszewski, T. Jung, J. Koh, I. Yuanying Deng, V.
Sarda, O. Moreira-Tamayo, V. Mayega, R.Katz, O.
Friedman, O. EytanEliezer, E. de-Obaldia and P. T. Bal-
sara, “All-digital TX Frequency Synthesizer and Dis-
crete-time Receiver for Bluetooth Radio in 130-nm
CMOS,” IEEE J. Solid-State Circuits, Vol. 39, No. 12,
2004, pp. 2278-2291.doi:10.1109/JSSC.2004.836345
[7] R. B. Staszewski, D. Leipold, C.-M. Hung and P. T. Bal-
sara, “TDC–Based Frequency Synthesizer for Wireless
Applications,” IEEE RFIC Symposium, 2004, pp.
215-218.
[8] J. Zhuang, K. Waheed and R. B. Staszewski, “A Tech-
nique to Reduce Phase/Frequency Modulation Bandwidth
in a Polar RF Transmitter,” IEEE Transactions on Cir-
cuits System I, Reg. Papers, Vol. 57, No. 9, 2010, pp.
2196-2207.
[9] I. Syllaios, P. Balsara and R. Staszewski, “Recombination
of Envelope and Phase Paths in Wideband Polar Trans-
mitters,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol.
57, No. 8, 2010, pp. 1891-1904.