ABSTRACT

We introduce a fast automatic sizing algorithm for a single-ended narrow-band CMOS cascode LNA adopting an inductive source degeneration based on an analytical approach without any optimization procedure. Analytical expressions for principle parameters are derived based on an ac equivalent circuit. Based on the analytical expressions and the power-constrained noise optimization criteria, the automatic sizing algorithm is developed. The algorithm is coded using Matlab, which is shown capable of providing a set of design variable values within seconds. One-time Spectre simulations assuming usage of a commercial 90 nm CMOS process are performed to confirm that the algorithm can provide the aimed first-cut design with a reasonable accuracy for the frequency ranging up to 5 GHz. This work shows one way how accurate automatic synthesis can be done in an analytical approach.

1. Introduction

In the field of RF transceiver design, there is a strong demand to digitalize even RF analog parts to mount a transceiver on a single chip [1,2] to utilize the capability of automatic synthesis in digital circuit design. However, the low noise amplifier (LNA), which is a critical building block in any RF front-end, is not ready for digitalization yet. Many efforts have been done for design automation of LNA beforehand since the design of LNA is a time-consuming task that typically relies heavily on the experience of RF designers. LNA design automation can significantly simplify the design task, and also opens a possibility towards digitalization.

There are two basic methods for LNA design automation: simulation based or equation based. Although the simulation-based methods [3,4] are more accurate, they are time consuming due to optimization procedures. On the other hand, equation-based methods [5-7] are faster, but are dependent on the accuracy of the models used. To overcome the disadvantages in some extent, advanced methods using both of equation-based and simulationbased approaches [8-10] have been also suggested.

The difficulties in design automation of LNA lie in several aspects. It is topology dependent, and the design itself is difficult involving trade-offs among critical figures of merits such as NF, power gain, impedance matching, power consumption, linearity, and stability. Mentioning the difficulties in a manual design, for example, even only for input and output matching, many iteration steps are needed. It should be also redesigned every time when the fabrication process is changed. Therefore it is desirable if the first-cut design synthesis can be done automatically and fast with an acceptable accuracy.

The purpose of this work is to suggest a methodology for providing a set of first-cut design variables for a narrow-band LNA with a reasonable accuracy once design and process specifications are given.

We introduce a speedy automatic sizing algorithm for a single-ended narrow-band cascode LNA adopting inductive source degeneration based on an analytical approach without any optimization procedure. In Section 2, design assumptions are discussed. In Section 3, analytical expressions for principle parameters are derived based on an ac equivalent circuit assuming a resistive output termination. In Section 4, the developed automatic sizing algorithm is explained in detail. In Section 5, verifications are given to check the accuracy of the automatic sizing results.

2. Design Assumptions

There are many topologies for narrow-band LNAs, however, typical topologies include cascode, common source, and differential configurations, and the cascode structure with an inductive source degeneration shown in Figure 1 is the most attractive one in single-ended topologies since it gives smaller input capacitance and larger in-out isolation [11]. In this work, the cascode LNA topology shown in Figure 1 is chosen as the objective circuit for automatic sizing even though the same approach can be applied to the other topologies.

There are several assumptions made in this work as follows:

1) Narrow-band LC matching networks are used for input and output as shown in Figure 1. R₁ is used to provide capability for adjusting power gain. As the output termination, two cases are considered: resistive or capacitive termination.

2) For sizing of the MOS transistors M₁ and M₂, the power-constrained noise optimization (PCNO) criteria [11] is adopted to trade off noise performance against power consumption.

3) Ideal inductors and capacitors are used by assuming usage of off-chip components. The series resistances of the on-chip inductors can be considered as well, but we choose a simpler case.

4) A current-mirror biasing is adopted as shown in Figure 1.

5) The widths of M₁ and M₂ are set as same.

6) The design specifications include operating frequency, input and output terminations, power consumption, power gain, and sufficiently low input and output reflection coefficients S₁₁ and S₂₂.

7) The design variables include L_g, L_s, L₁, C_i, C_o, R₁, R_DB, and R_B including the widths of M₁, M₂, and M_B in Figure 1.

3. Derivation of Analytic Expressions for Principal Parameters

3.1. Input Impedance

Figure 2 is the whole ac equivalent circuit for the cascode LNA shown in Figure 1 including the input signal source and the output resistive termination. We note that, compared to the complete equivalent circuit of the BSIM4 NMOS transistor in SPICE, only the back-gate transconductance g_mb and the gate-body capacitance C_gb in the transistor model are ignored to simplify the analysis. The distributed resistances including R_s, R_d, R_g, and R_sub, which are included in the BSIM 4 transistor model, are also ignored since they are negligible in large transistors.

In Figure 2, g_m1 and g_m2 denote the transconductances of M₁ and M₂, respectively. C_gs, C_gd, and C_ds denote the gate-source, gate-drain, and drain-source capacitances of the NMOS transistors, respectively. C_js and C_jd denote the source-body and drain-body junction capacitances, and C_L is equal to the sum of C_dg2 and C_jd2, which are the

capacitances present at the drain node of M₂ in Figure 1.

The impedances Z_in, Z_in1, Z_in2, Z_o, Z_out, Z_out1, and Z_out2 are self-defined in the circuit. We first consider the resistive output termination case and discuss the capacitive output termination case later in Section 6. We note that C_gs, C_gd, and C_ds are replaced by C_sg, C_dg, and C_sd, respectively, in some part of our derivations for input and output impedances considering the non-reciprocal nature of gate-oxide capacitances in the BSIM4 MOSFET capacitance model [12].

First, we derive Z_in by deriving Z_o, Z_in2, and Z_in1 in order. We note that, we use s and jω without differentiation since we are dealing with ac response only.

To derive Z_o at the operating frequency, the series C_o and R_so in Figure 2 can be transformed to the parallel equivalents, C_p and R_p [11]. Then Y_o = 1/Z_o is simply expressed as

, (1)

where R_p = R_so(Q² + 1), C_p = C_oQ²/(Q² + 1), and Q = 1/(ωR_soC_o).

Figure 3 shows the ac equivalent circuit to derive an expression for Z_in2. Notice that, in the circuit shown in Figure 3, the non-reciprocal capacitance C_sd2 is used instead of C_ds2, since we are looking into the source of M₂.

By neglecting the parallel (C_sg2 + C_js2) branch, we derive the input admittance Y_in21 first, and add s(C_sg2 + C_js2) to find Y_in2 = 1/Z_in2. When the (C_sg2 + C_js2) branch is neglected, the circuit can be characterized by (2) and (3).

(2)

(3)

By eliminating v_o in (2) and (3), we can express Y_in21 as

, (4)

where Z_p = (1/sC_L)//R₁//Z_o.

Then Y_in2 are expressed as

. (5)

Figure 4 shows the ac equivalent circuit to derive an expression for Z_in1. The circuit can be characterized by (6), (7), and (8).

(6)

(7)

, (8)

where Z_L = (1/(sC_jd1))//Z_in2.

By eliminating v_s1 and v_s2 in (6), (7) and (8), Y_in1 = 1/Z_in1 is expressed as

, (9)

where,

,

,

and.

Then Z_in is expressed as

. (10)

3.2. Output Impedance

Z_out derivation can be done similarly as the Z_in derivation using the equivalent circuit in Figure 2 assuming R_si input termination. We present the results only here.

Y_out2 = 1/Z_out2 is expressed as

, (11)

where,

,

,

and

Y_out1 = 1/Z_out1 is expressed as

, (12)

where and.

Then Z_out is expressed as

. (13)

3.3. Power Gain

To derive the LNA voltage gain, the equivalent circuit in Figure 2 is simplified into the one shown in Figure 5,

where the whole circuit is expressed as a 3-stage cascaded amplifier.

Z_in1, Z_in2 and Z_o in Figure 5 are already derived in (9), (5) and (1), respectively. Notice that A₁v_g1, gZ_out2, A₂v_s2, and gZ_out1 are the Thevenin equivalent voltages and impedances of the 2^nd and 3^rd gain stages in Figure 2. Therefore gZ_out2 and gZ_out1 differ from Z_out2 and Z_out1 in (11) and (12), respectively, and can be derived as follows.

By definition, gZ_out2 corresponds to the impedance seen to the left of the v_s2 node when v_g1 = 0 in Figure 2, and can be derived using the equivalent circuit shown in Figure 6.

The circuit can be characterized by the Equations (14) and (15).

(14)

(15)

By eliminating v_s1 in (14) and (15), gY_out21 is expressed as

(16)

Then gY_out2 =1/gZ_out2 is expressed as

. (17)

By definition, A₁ corresponds to the voltage gain v_s2o/v_g1, where v_s2o is the v_s2 node voltage when open, and can be derived using the equivalent circuit shown in Figure 7. The circuit can be characterized by the Equations (18) and (19).

(18)

(19)

By eliminating v_s1 in (18) and (19), we get

(20)

where and

.

gZ_out1 corresponds to the impedance seen to the left of the v_o node with v_s2 = 0 in Figure 2. Since g_m2v_s2 and (C_gs2 + C_js2) do not function when v_s2 = 0, gY_out1 = 1/gZ_out1 is simply expressed as

. (21)

A₂ corresponds to the voltage gain v_oo/v_s2, where v_oo is the v_o node voltage when open, and A₂ derivation can be done in the similar fashion to the one for A₁ derivation. The resulting A₂ is expressed as

. (22)

In Figure 2, the available input power P_i, which is supplied to the LNA when impedance matched, is defined as

. (23)

The maximum output power P_o, which is supplied to the resistive load R_so when impedance matched, is expressed as

, (24)

where v_o and v_out are defined in Figure 2, and R_p is the transformed parallel resistance of R_so, which is already defined relating (1).

Then the available power gain G is expressed as

(25)

where A_v1, A_v2, and A_v3 can be easily derived from Figure 5 as follows.

(26)

(27)

(28)

4. Automatic Sizing Algorithm

Figure 8 shows the automatic sizing algorithm developed in this work. The inputs to the algorithm include design and process specifications, and the outputs include synthesized design variable values are for R_DB, W, nfb, L_s, L_g, C_i, R₁, L₁, C_o. Here, we explain the procedures from top to bottom in accordance with each step, which is explicitly indicated in Figure 8.

4.1. 1^st Step: Entering Design and Process Specifications

The 1^st step in the automatic sizing is to enter the design

and process specifications. The design specifications include the operating frequency f, the input output terminations R_si and R_so, the supply current I_DD, the desired power gain Gain_design. Instead of I_DD, the power consumption PWR and the supply voltage V_DD can be entered to calculate I_DD by PWR/V_DD. The process specifications include the transistor channel length L, the transistor channel width per finger WF, and the maximum finger number nf_max defined for one unit of transistors.

4.2. 2^nd Step: Calculation of Optimum Transistor Width

The next step is to calculate the transistor channel width W for optimum noise performance. The width for optimum noise performance is usually too large for practical use, and therefore the power-constrained noise optimization (PCNO) device width W_optP [11] is adopted as W in this work. W_optP is calculated according to the last rough equation in (29).

(29)

As shown in (29), W_optP increases continuously as the frequency decreases. Therefore it may be necessary to define a maximum value for W considering lower frequency design. We suggest to limit W below 1000 μm.

If W_F and nf_max are defined, the finger number nf is first calculated as W/W_F, and the number of the maximum-fingered units m is calculated as the integer value of nf/nf_max, and the residual finger number nf_residue is determined as the residue to give an information for the transistor layout. Then the final W is determined by W = W_F × (m × nf_max + nf_residue). We note that W_F and nf_max are usually defined in most of recent processes.

4.3. 3^rd Step: Calculation of Bias Circuit Design Variables and Getting DC Operating Point Information

The next step is to determine the bias circuit variable values and to get the dc operating point information.

The finger number for the bias transistor nfb and the drain bias resistance R_DB in Figure 1 should be determined. By limiting the bias circuit current around 100 μA, for example, we can determine nfb by nfb = (100 μA/I_DD) × nf. For the decoupling resistor R_B, we can simply use 5 kΩ, which is a reasonable value.

The next procedure is to determine R_DB, which, however, is very difficult to determine by calculation. Since I_DD is sensitive to the value of R_DB, it should be manually determined to give the specified I_DD value by dc circuit simulations. This procedure is one obstacle against full design automation in this work. However, it is an essential procedure since it provides the accurate operating point information to proceed with the remaining part of the design automation. The needed operating point information include the values of g_m, g_ds, C_gs, C_sg, C_gd, C_dg, C_ds, C_sd, C_js, and C_jd of M₁ and M₂ in Figure 1, which should be imported into the automatic sizing algorithm.

4.4. 4^th Step: Iterations to Determine Design Variable Values

There are three main iteration loops in the automatic sizing algorithm as shown in Figure 8. The 1^st loop finds G_max, which corresponds to the case with the upper limit of R₁, which is chosen arbitrarily large enough as 10 kΩ in this work. To find G_max, we need to find all the design variable values for the G_max case simultaneously. Iteration is needed since the input and output matching designs affect each other. The 2^nd loop finds G_min, which corresponds to the case with the lower limit of R₁, which is arbitrarily chosen small as 40 Ω in this work to allow a larger allowable gain range. This iteration is also needed for the same reason explained for the G_max case. The 3^rd loop finds the proper R₁ value for the desired gain Gain_ design by the bisection method, which lies within the lower and upper boundaries G_min and G_max, and its inner loop finds the corresponding design variable values for the present gain value during iteration similarly as in the 1^st and 2^nd iteration loops.

4.4.1. Iterations to Solve for the G_max Case

As explained above, Z_in1 is affected by output matching design, and Z_out is affected by input matching design. Therefore we need some iteration to determine L_s. Since Z_in2 is affected by Z_o, which is unknown yet, we need an initial guess for Z_o to find the 1^st L_s value. As shown in Figure 8, an initial guess for Z_oL = Z_o//(1/sC_L) is given as 50/g·m², which is shown to be large enough for all possible situations in the procedure, to solve for Z_in2 by (5).

The impedance seen at the gate of M₁ is equal to Z_in1, which is derived in (9). By setting the real part of Z_in1 Re(Z_in1) equal to R_si for input impedance matching, we can find L_s. However this equation Re(Z_in1) = R_si is too complicated to get the solution directly with the other present design variables values given, and therefore L_s is solicited numerically within the lower and upper boundaries of 0.1 nH and 5 nH. We use the bisection method for this purpose.

The next procedure is to calculate L_g and C_i, which nullify the imaginary part of Z_in1 Im(Z_in1) in Figure 2. Z_in1 is usually capacitive to give a negative value for Im(Z_in1), and therefore L_g can be calculated using the equation Im(Z_in1) – 1/(ωC_i) + ωL_g = 0, where C_i is simply a large dc blocking capacitor. We first calculate L_g1, which nullifies Im(Z_in1) using Im(Z_in1) + ωL_g1 = 0. Although C_i is larger the better, considering the layout size, 1/(ωC_i) = ωL_g1/10 is used to determine C_i. L_g is then recalculated using Im(Z_in1) – 1/(ωC_i) + ωL_g = 0.

Depending on to the operating frequency and the desired gain, Z_in1 may happen to be inductive, or this situation can happen in the middle of the iterations. For this case, a nominal single bond wire inductance of 1 nH is assumed for L_g and Im(Z_in1) – 1/ωC_i + ωL_g = 0 is used to calculate the required C_i value.

In the next procedure, the design variables L₁ and C_o are determined using the equations Re(Z_out) = R_so and Im(Z_out) = 0 for output impedance matching to R_so, where Re(Z_out) is the real part of Z_out expressed in (13).

If we let Z_out1 in (12) equal to A + jB, the real and imaginary parts of Z_out1//jωL₁ in (13) are expressed as

(30)

Then by letting Re(Z_out) = Re(Z_out1//jωL₁) = R_so, L₁ is expressed as

(31)

By letting Im(Z_out) = Im(Z_out1//jωL₁) – 1/(ωC_o) = 0, C_o is expressed as

. (32)

Using (31) and (32), L₁ and C_o can be simply calculated.

Now the 1^st set of the design variable values are ready to update Z_oL and the remaining iterations are performed to find the final design variable values for the G_max case. It was found that the iteration number for this loop should be larger than 10.

Right after the iteration loop, A₁, gZ_out2, A₂, and gZ_out1 are calculated using (20), (17), (22), and (21), respectively, and G_max is calculated using (25).

If the G_max value is smaller than the desired gain, the routine gives a warning and stops.

4.4.2. Iterations to Solve for the G_min Case

The 2^nd loop finds the design variable values for the G_min case. The same iteration as above with the last Z_oL value as an initial guess is performed to find G_min using (25) again.

4.4.3. Iterations to Solve for the Gain_Design Case

The 3^rd loop finds the proper R₁ value for the desired gain Gain_design using the bisection method while the inner loop finds the corresponding design variable values for the present gain value. This inner iteration loop is exactly same as the 1^st and 2^nd loops. After all the design variables are determined for the present gain value, the gain is calculated using (25) again. If the calculated gain is equal to Gain_design within the allowed tolerance, the calculation stops to output the final set of the design variable values, which include W, nf, m, nf_residue, nfb, L_s, L_g, C_i, R₁, L₁, and C_o.

5. Verifications

The automatic sizing algorithm explained in Section 4 was coded using Matlab (Version 7.9.0.529) assuming usage of a 90 nm commercial CMOS process. The design variable sets for seven different operating frequencies ranging from 0.7 GHz to 5 GHz were synthesized, and verifications were done by one-time Spectre circuit simulations with the corresponding BSIM4.5.0 MOSFET model [12] for the assumed process.

The design specifications include I_D = 5 mA, V_DD = 1.2 V, Gain_design = 21 dB, and R_si = R_so = 50 Ω. The process specifications include L = 75 nm, W_F = 3 μm, and nf_max = 64, where 75 nm for L is the effective channel length in this process. The maximum transistor width was set as W_max = nf_max × m × W_F = 64 × 5 × 3 μm = 960 μm, which is below 1000 μm as we suggested.

As examples of the verifications, Figures 9 and 10 show the simulated LNA characteristics without any tuning for the operating frequency of 1 GHz and 5 GHz, respectively, when the corresponding sets of the design variable values obtained using the automatic sizing algorithm are used for the simulations. The synthesized design variable values are as follows;

For 1 GHz design, R_DB = 12.7 kΩ, W = 960 μm (m = 5, nf_residue = 0), nfb = 6, L_s = 1.382 nH, L_g = 19.557 nH, C_i = 14.25 pF, R₁ = 497.1 Ω, L₁ = 11.904 nH, C_o = 1.447 pF.

For 5 GHz design, R_DB = 5.96 kΩ, W = 231 μm (m = 1, nf_residue = 13), nfb = 2, L_s = 0.5383 nH, L_g = 2.690 nH, C_i = 4.142 pF, R₁ = 1.752 kΩ, L₁ = 2.813 nH, C_o = 0.190 pF.

Table 1 summarizes the simulated results of the seven designs, which reside in the frequency range, where the automatic sizing program could provide the design variable set for Gain_design of 21 dB. Notice that, for the operating frequencies below 1 GHz, the synthesized W values are restricted to below 960 μm, which is equal to the value for W_max.

In Table 1, we can see that the input and output matchings (S₁₁ and S₂₂) are pretty good for all the designs, and the noise figure is pretty close to the noise figure minimum, which demonstrates the adequacy of the designs.

We note that power gain values are about the same with S₂₁ values. The S₂₁ values in Table 1 are smaller than the desired gain of 21 dB. This seems to be caused by neglecting g_mb, C_gb, R_s, R_d, R_g, and R_sub in the equivalent circuit in Figure 2. However we believe that the result is pretty good for the first-cut quick design.

Table 2 summarizes the synthesized available gain ranges with the corresponding R₁ values for each design. We can see that a wide range of power gain can be obtained by varying the R₁ values as expected.

6. Conclusions

The analytical expressions for the principle parameters

were derived using the ac equivalent circuit of the singleended narrow-band cascode CMOS LNA adopting the inductive source degeneration. Based on the expressions, the automatic sizing algorithm was developed by adopting the power-constrained noise optimization criteria. The algorithm was coded using Matlab, and could provide a set of design variable values within seconds. One-time Spectre simulations without any tuning assuming usage of a commercial 90 nm CMOS process were performed to confirm that the automatic sizing program can synthesize the aimed first-cut design with a reasonable accuracy for the frequency range reaching up to 5GHz.

This work showed in detail how the accurate automatic sizing can be done in an analytical approach. The approach can be applied to a common source LNA more easily since the derivation of principal parameters will be simpler with a fewer gain stages. It can be also applied to a differential LNA easily since the derivation will be basically same. The approach seems applicable to more complicated designs even though the derivation procedures will contain enhanced complexity.

The automatic sizing program may be utilized efficiently for additional tuning purpose. For example, after examining the first-cut synthesis result with verifying circuit simulations, a smaller value for W_M2 compared to the synthesized one for W_M1 can be entered into the automatic sizing program to obtain another design variable set for better linearity.

REFERENCES

NOTES

^*This work was supported by 2011 Hongik University Research Fund (sponsors).