S. RAI ET AL. 21
plored [9]. In mixed mode integrated circuits the crucial
parameters that affect the performance of the digital sys-
tem are supply noise and substrate noise. Source coupled
logic (SCL) are widely used to reduce the output voltage
swing compared to CMOS logic gates for high frequency
application. This paper explores performance comparison
of two source coupled logic structures with previously
available Sub Threshold Source Coupled Logic (STSCL)
gates for implementing ultra-low-power digital systems.
In this approach, the power consumption and maximum
speed of operation can be adjusted linearly through the
tail bias current of each gate over a very wide range
[11,12], thus, efficiently decoupling the decision of out-
put voltage swing from power dissipation and delay. To
enable the operation at very low trail bias current and to
achieve the desired performance, we have to use a spe-
cial circuit technique for implementing very low power
Source Coupled Logic circuit. In first design, the intrin-
sically limited output impedance of deep-submicron, dy-
namic threshold PMOS devices have been used to im-
plement very high value load resistances for SCL topol-
ogy. In second design an active load current mirror has
been used to implement very high value of load resis-
tance called Current Mirror Source Coupled Logic
(CMSCL). Here, a more general approach with much
less sensitivity to process and technology variations will
be introduced [12]. This paper presents two different
techniques, one for implementing Dynamic Threshold
Source Coupled Logic (DTSCL) gates where the bias
current of each cell can be set as low as 0.1 pA and an-
other for implementing Current Mirror source coupled
logic gates where the bias current of each cell can be set
as high as 1 mA. In Section 2, after a brief review of SCL
circuits, the proposed techniques for implementing dif-
ferent SCL gates will be introduced. Section 3 discusses
about the load device concept applied to SCL circuits.
Section 4 discusses about the experimental results and
implementation of the proposed circuits. Section 4.4 dis-
cusses the power-delay performance of the proposed cir-
cuit configurations and comparison of different SCL
logic structures, followed by conclusions in Section 4.5
and finally Acknowledgement in Section 5.
2. Different Source-Coupled Logic Structure
2.1. DTMOS Topology
In DTMOS logic, gates of transistors are tied to their
substrates to achieve the same stability with direct sub-
strate biasing without using additional control circuitry as
in case of VTCMOS logic (Figure 1) [11]. As the sub-
strate voltage in DTMOS logic changes with the gate
input voltage, the threshold voltage is dynamically
changed. In the off-state, i.e., ininDD for
NMOS (PMOS), the characteristics of DTMOS transistor
is exactly the same as regular MOS transistor. Both have
the same properties, such as the same off-current, sub-
threshold slope, and threshold voltage. In the on-state,
however, the substrate-source voltage (Vbs) for NMOS
(PMOS), the characteristics of DTMOS transistor is ex-
actly the same as regular MOS transistor. When the
DTMOS is in off state then it offers higher threshold
voltage which in turn reduces the leakage current of the
MOS device. In the on state, the substrate-source voltage
(Vbs) increases which in turn reduces threshold voltage of
the DTMOS. Reduction in threshold voltage is due to the
reduction in body charge which again leads to an advan-
tage of higher carrier mobility because the reduced body
charge causes a lower effective normal field. The re-
duced threshold, lower normal effective electric field,
and higher mobility results in higher on current drive in
DTMOS than that of a simple MOS transistor.
The sub-threshold slope of DTMOS improves and ap-
proaches the ideal 60 mV/decade which makes it more
efficient in sub threshold logic circuits to obtain higher
gain.
2.2. Current Mirror Topology
A current mirror is a circuit designed to copy a current
through one active device by controlling the current in
another active device of a circuit, keeping the output
current constant regardless of loading. The current being
‘copied’ can be, and sometimes is, a varying signal cur-
rent. Conceptually, an ideal current mirror is simply an
ideal current amplifier. The current mirror is used to pro-
vide bias currents and active loads to circuits. High-per-
formance current mirrors with low input and output
voltages are required as building blocks of mixed-mode
VLSI systems that operate from a single supply of 1.8 V
or below. High accuracy requires very high output resis-
tance and low input resistance. Low-voltage operation
requires low input and output voltages as well as low
supply requirements for the control circuitry used to im-
prove the mirror’s input and output resistance. There are
three main specifications that characterize a current mir-
ror. The first is the current level it produces. The second
is its AC output resistance, which determines how much
the output current varies with the voltage applied to the
mirror. The third specification is the minimum voltage
drop across the mirror necessary to make it work prop-
erly. This minimum voltage is dictated by the need to
keep the output transistor of the mirror in active mode.
0VVV DT-PMOS
DT-NMOS
Figure 1. DT-NMOS and DT-PMO S.
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